| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VECustomDAG.cpp | 64 case ISD::MLOAD: in getVVPOpcode()
205 case ISD::MLOAD: in getMaskPos()
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| H A D | VEISelLowering.cpp | 346 for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE}) in initVPUActions()
1941 case ISD::MLOAD: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1279 MLOAD, enumerator
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| H A D | SelectionDAGNodes.h | 1447 case ISD::MLOAD:
2668 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2671 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2687 return N->getOpcode() == ISD::MLOAD ||
2700 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2715 return N->getOpcode() == ISD::MLOAD;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 139 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
179 setOperationAction(ISD::MLOAD, P, Custom); in initializeHVXLowering()
222 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
290 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
2178 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
2180 if (Opc == ISD::MLOAD) { in LowerHvxMaskedOp()
3008 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
3015 if (MemOpc == ISD::MLOAD) { in SplitHvxMemOp()
3151 case ISD::MLOAD: in LowerHvxOperation()
3229 case ISD::MLOAD: in LowerHvxOperation()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 408 case ISD::MLOAD: return "masked_load"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 82 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N)); in PromoteIntegerResult()
1807 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N), in PromoteIntegerOperand()
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| H A D | LegalizeVectorTypes.cpp | 1025 case ISD::MLOAD: in SplitVectorResult()
4109 case ISD::MLOAD: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 856 case ISD::MLOAD: { in AddNodeIDCustom()
9354 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops); in getMaskedLoad()
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| H A D | DAGCombiner.cpp | 2048 case ISD::MLOAD: return visitMLOAD(N); in visit()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1455 case ISD::MLOAD: in SelectT2AddrModeImm7Offset()
4016 case ISD::MLOAD: in Select()
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| H A D | ARMISelLowering.cpp | 265 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
339 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
10641 case ISD::MLOAD: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1308 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1408 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1454 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1525 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1898 setOperationAction(ISD::MLOAD, VT, Custom); in addTypeForFixedLengthSVE()
6337 case ISD::MLOAD: in LowerOperation()
20295 return OC == ISD::LOAD || OC == ISD::MLOAD || in isCheapToExtend()
20781 if (N->getOperand(0).getOpcode() == ISD::MLOAD && in performUnpackCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 715 def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 837 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
975 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1169 {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom); in RISCVTargetLowering()
1281 setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE, in RISCVTargetLowering()
6471 case ISD::MLOAD: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1568 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
1778 setOperationAction(ISD::MLOAD, VT, Custom); in X86TargetLowering()
1952 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
1959 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
2085 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2458 ISD::MLOAD, in X86TargetLowering()
31996 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG); in LowerOperation()
56197 case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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