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Searched refs:MIMG (Results 1 – 14 of 14) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td95 def MIMG {
197 let MIMG = 1;
225 let MIMG = 0;
230 let MIMG = 0;
1522 // MIMG Instructions
1543 defm IMAGE_ATOMIC_RSUB : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP, 0x13…
1554 defm IMAGE_ATOMIC_FMIN : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x1e, MIMG.NOP>, "image_…
1555 defm IMAGE_ATOMIC_FMAX : MIMG_Atomic <mimgopc<MIMG.NOP, MIMG.NOP, 0x1f, MIMG.NOP>, "image_…
1556 defm IMAGE_ATOMIC_PK_ADD_F16 : MIMG_Atomic <mimgopc<0x86, MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP…
1557 defm IMAGE_ATOMIC_PK_ADD_BF16 : MIMG_Atomic <mimgopc<0x87, MIMG.NOP, MIMG.NOP, MIMG.NOP, MIMG.NOP…
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H A DSILoadStoreOptimizer.cpp81 MIMG, enumerator
182 return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset; in operator <()
434 return MIMG; in getInstClass()
757 if (InstClass == MIMG) { in setMI()
773 } else if (InstClass != MIMG) { in setMI()
884 assert(CI.InstClass == MIMG); in dmasksCanBeCombined()
960 assert(CI.InstClass != MIMG); in offsetsCanBeCombined()
1140 if (CI.InstClass == MIMG) { in checkAndPrepareMerge()
1826 case MIMG: in getNewOpcode()
1836 assert((CI.InstClass != MIMG || in getSubRegIdxs()
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H A DSIPostRABundler.cpp61 SIInstrFlags::FLAT | SIInstrFlags::MIMG;
H A DSIInstrFormats.td42 field bit MIMG = 0;
191 let TSFlags{20} = MIMG;
H A DAMDGPUInsertDelayAlu.cpp46 SIInstrFlags::FLAT | SIInstrFlags::MIMG | in instructionWaitsForVALU()
H A DSIDefines.h83 MIMG = 1 << 20, enumerator
H A DSIInstrInfo.h581 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()
585 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
H A DAMDGPU.td233 "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
239 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
H A DSIInstrInfo.cpp5428 (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG)))) { in adjustAllocatableRegClass()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp273 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()
307 MCID.TSFlags & SIInstrFlags::MIMG; in isVMEM()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp359 if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { in encodeInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp776 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { in getInstruction()
1038 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc in convertMIMGInst()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3687 SIInstrFlags::MIMG | SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE;
3749 int RSrcOpName = Desc.TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc in validateMIMGAddrSize()
4560 SIInstrFlags::MTBUF | SIInstrFlags::MIMG | in validateAGPRLdSt()
4756 SIInstrFlags::MTBUF | SIInstrFlags::MIMG | in validateCoherencyBits()
4772 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { in validateCoherencyBits()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td620 bit DA = 0; // DA bit in MIMG encoding