| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 403 if (!GetImm(MI2, 2, Offset2)) in ConsecutiveInstr()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
465 MachineInstr *MI2 = &*NextMII; in ReduceXWtoXWP() local
622 MachineInstr *MI2 = &*NextMII; in ReduceMoveToMovep() local
633 if (MI2->getOpcode() != Entry.WideOpc()) in ReduceMoveToMovep()
738 MIB.add(MI2->getOperand(0)); in ReplaceInstruction()
741 MIB.add(MI2->getOperand(1)); in ReplaceInstruction()
745 MIB.add(MI2->getOperand(0)); in ReplaceInstruction()
747 MIB.add(MI2->getOperand(1)); in ReplaceInstruction()
751 MIB.add(MI2->getOperand(2)); in ReplaceInstruction()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 475 MachineInstr *MI2 = *I2; in hoistAndMergeSGPRInits() local
510 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
511 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
514 << printMBBReference(*MI2->getParent()) << " " << *MI2); in hoistAndMergeSGPRInits()
515 MergedInstrs.insert(MI2); in hoistAndMergeSGPRInits()
520 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
521 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
532 MI2->getParent()); in hoistAndMergeSGPRInits()
539 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
544 << printMBBReference(*MI2->getParent()) << " to " in hoistAndMergeSGPRInits()
[all …]
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| H A D | SIInstrInfo.cpp | 521 const MachineInstr &MI2, in memOpsHaveSameBasePtr() argument
529 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
533 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 272 const MachineInstr &MI2, in alias() argument
274 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
278 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias()
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| H A D | TargetInstrInfo.cpp | 842 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
846 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
849 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB); in hasReassociableOperands()
862 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
868 areOpcodesEqualOrInverse(Opcode, MI2->getOpcode()); in hasReassociableSibling()
870 std::swap(MI1, MI2); in hasReassociableSibling()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 277 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply() local
278 if (!QII->isHVXVec(MI2)) in apply()
280 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) { in apply()
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| H A D | HexagonVLIWPacketizer.h | 144 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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| H A D | HexagonInstrInfo.h | 408 const MachineInstr &MI2) const;
420 const MachineInstr &MI2) const;
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| H A D | HexagonVLIWPacketizer.cpp | 967 MachineInstr &MI2) { in arePredicatesComplements() argument
971 getPredicateSense(MI2, HII) == PK_Unknown) in arePredicatesComplements()
1024 unsigned PReg2 = getPredicatedRegister(MI2, HII); in arePredicatesComplements()
1028 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1029 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
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| H A D | HexagonInstrInfo.cpp | 2687 const MachineInstr &MI2) const { in isToBeScheduledASAP()
2691 int N = MI2.getNumOperands(); in isToBeScheduledASAP()
2693 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg()) in isToBeScheduledASAP()
2696 if (mayBeNewStore(MI2)) in isToBeScheduledASAP()
2697 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi) in isToBeScheduledASAP()
2698 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2699 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3035 const MachineInstr &MI2) const { in addLatencyToSchedule()
3036 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
3037 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
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| H A D | HexagonPatterns.td | 876 class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
878 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 277 const MachineInstr &MI2, unsigned N2) const;
399 const MachineInstr &MI2, in getAddrDispShift() argument
402 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
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| H A D | X86ISelLowering.h | 1757 MachineInstr &MI2,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 314 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
318 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.h | 63 bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2,
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | DFAPacketizer.h | 215 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 105 const MachineInstr &MI2, in aliasIsKnownForLoadStore() argument
109 auto *LdSt2 = dyn_cast<GLoadStore>(&MI2); in aliasIsKnownForLoadStore()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 293 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
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| H A D | RISCVInstrInfo.cpp | 2245 const MachineInstr &MI2, in memOpsHaveSameBasePtr() argument
2253 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
2257 auto MO2 = *MI2.memoperands_begin(); in memOpsHaveSameBasePtr()
3278 bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) { in hasEqualFRM() argument
3282 RISCV::getNamedOperandIdx(MI2.getOpcode(), RISCV::OpName::frm); in hasEqualFRM()
3286 MachineOperand FrmOp2 = MI2.getOperand(MI2FrmOpIdx); in hasEqualFRM()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 1655 auto MI2 = in expandLSLW4Rd() local
1661 MI2->getOperand(3).setIsDead(); in expandLSLW4Rd()
1853 auto MI2 = in expandLSRW4Rd() local
1859 MI2->getOperand(3).setIsDead(); in expandLSRW4Rd()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | AsmPrinter.cpp | 1758 auto MI2 = std::next(MI.getIterator()); in emitFunctionBody() local
1759 if (IsEHa && MI2 != MBB.end() && in emitFunctionBody()
1760 (MI2->mayLoadOrStore() || MI2->mayRaiseFPException())) in emitFunctionBody()
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