Home
last modified time | relevance | path

Searched refs:MHz (Results 1 – 25 of 359) sorted by relevance

12345678910>>...15

/freebsd-14.2/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
H A Dstmpe.txt28 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
29 1 -> 3.25 MHz
/freebsd-14.2/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-tmu.dtsi56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
248 /* Set maximum frequency as 900MHz */
[all …]
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
297 /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
H A Drk3288-veyron-mickey.dts86 * and don't let the GPU go faster than 400 MHz.
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
139 /* At very hot, don't let GPU go over 300 MHz */
180 /* After 1st level throttle the GPU down to as low as 400 MHz */
200 /* When hot, GPU goes down to 300 MHz */
206 /* When really hot, don't let GPU go _above_ 300 MHz */
H A Dexynos5422-odroid-core.dtsi45 /* derived from 532MHz MPLL */
71 /* derived from 666MHz CPLL */
89 /* derived from 666MHz CPLL */
101 /* derived from 600MHz DPLL */
116 /* derived from 666MHz CPLL */
137 /* derived from 532MHz MPLL */
155 /* derived from 666MHz CPLL */
164 /* derived from 666MHz CPLL */
185 /* derived from 532MHz MPLL */
203 /* derived from 600MHz DPLL */
[all …]
/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dsamsung,exynos850-clock.yaml71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
165 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
201 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
249 - description: External reference clock (26 MHz)
[all …]
H A Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
70 - description: External reference clock (26 MHz)
86 - description: External reference clock (26 MHz)
104 - description: External reference clock (26 MHz)
122 - description: External reference clock (26 MHz)
142 - description: External reference clock (26 MHz)
164 - description: External reference clock (26 MHz)
186 - description: External reference clock (26 MHz)
206 - description: External reference clock (26 MHz)
226 - description: External reference clock (26 MHz)
H A Dtesla,fsd-clock.yaml16 The root clock comes from external OSC clock (24 MHz).
56 - description: External reference clock (24 MHz)
70 - description: External reference clock (24 MHz)
90 - description: External reference clock (24 MHz)
114 - description: External reference clock (24 MHz)
134 - description: External reference clock (24 MHz)
152 - description: External reference clock (24 MHz)
166 - description: External reference clock (24 MHz)
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
H A Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
/freebsd-14.2/sys/contrib/device-tree/Bindings/media/i2c/
H A Dsony,imx412.yaml34 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
H A Dsony,imx415.yaml31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
/freebsd-14.2/sys/contrib/device-tree/Bindings/display/bridge/
H A Dtoshiba,tc358767.txt8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
H A Dti,sn65dsi86.txt29 clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
/freebsd-14.2/sys/contrib/device-tree/Bindings/regulator/
H A Dmax8952.txt15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
H A Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
H A Dmps,mpq7920.yaml37 1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz
/freebsd-14.2/sys/contrib/device-tree/Bindings/usb/
H A Drockchip,dwc3.txt8 "ref_clk" Controller reference clk, have to be 24 MHz
9 "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
10 "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
11 operation and >= 30MHz for HS operation
H A Drockchip,dwc3.yaml54 Controller reference clock, must to be 24 MHz
56 Controller suspend clock, must to be 24 MHz or 32 KHz
58 Master/Core clock, must to be >= 62.5 MHz for SS
59 operation and >= 30MHz for HS operation
H A Drockchip,rk3399-dwc3.yaml27 Controller reference clock, must to be 24 MHz
29 Controller suspend clock, must to be 24 MHz or 32 KHz
31 Master/Core clock, must to be >= 62.5 MHz for SS
32 operation and >= 30MHz for HS operation
/freebsd-14.2/sys/contrib/device-tree/Bindings/net/
H A Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
/freebsd-14.2/sys/contrib/device-tree/Bindings/mips/cavium/
H A Ductl.txt29 /* 12MHz, 24MHz and 48MHz allowed */
/freebsd-14.2/sys/contrib/device-tree/src/powerpc/
H A Dmedia5200.dts29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
/freebsd-14.2/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dstmpe.txt53 0 -> 1.625 MHz
54 1 -> 3.25 MHz
55 2 || 3 -> 6.5 MHz
78 /* 3.25 MHz ADC clock speed */

12345678910>>...15