Home
last modified time | relevance | path

Searched refs:MERGE_VALUES (Results 1 – 23 of 23) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h236 MERGE_VALUES, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1902 case ExtractValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
1903 case InsertValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp181 case ISD::MERGE_VALUES: return "merge_values"; in getOperationName()
H A DLegalizeVectorOps.cpp300 case ISD::MERGE_VALUES: in LegalizeOp()
888 case ISD::MERGE_VALUES: in Expand()
H A DSelectionDAGBuilder.cpp948 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); in getCopyFromRegs()
3308 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, in visitLandingPad()
3631 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitSelect()
4054 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInsertValue()
4089 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitExtractValue()
4417 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, in visitLoad()
9766 if (Val.getOpcode() == ISD::MERGE_VALUES) { in visitInlineAsm()
9782 SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInlineAsm()
10664 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, in LowerCallTo()
11985 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitFreeze()
[all …]
H A DInstrEmitter.cpp1211 case ISD::MERGE_VALUES: in EmitSpecialNode()
H A DSelectionDAG.cpp3093 case ISD::MERGE_VALUES: in computeKnownBits()
4301 case ISD::MERGE_VALUES: in ComputeNumSignBits()
5642 case ISD::MERGE_VALUES: in getNode()
8321 return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops); in getMergeValues()
9867 return getNode(ISD::MERGE_VALUES, DL, VTList, {N1, ZeroOverFlow}, Flags); in getNode()
9877 return getNode(ISD::MERGE_VALUES, DL, VTList, in getNode()
9884 return getNode(ISD::MERGE_VALUES, DL, VTList, in getNode()
9919 return getNode(ISD::MERGE_VALUES, DL, VTList, {Lo, Hi}, Flags); in getNode()
9935 return getNode(ISD::MERGE_VALUES, DL, VTList, {Result0, Result1}, Flags); in getNode()
H A DLegalizeFloatTypes.cpp65 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
1292 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in ExpandFloatResult()
H A DScheduleDAGRRList.cpp708 case ISD::MERGE_VALUES: in EmitNode()
H A DLegalizeVectorTypes.cpp55 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
990 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in SplitVectorResult()
4073 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; in WidenVectorResult()
H A DLegalizeDAG.cpp1103 case ISD::MERGE_VALUES: in LegalizeOp()
3167 case ISD::MERGE_VALUES: in ExpandNode()
H A DLegalizeIntegerTypes.cpp58 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
2609 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in ExpandIntegerResult()
H A DTargetLowering.cpp10578 assert(Ret.getOpcode() == ISD::MERGE_VALUES && in expandMULO()
H A DDAGCombiner.cpp1924 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); in visit()
15011 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4276 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Flag); in lowerXALUO()
4314 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
4373 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Flag); in lowerUADDSUBO_CARRY()
4412 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerUADDSUBO_CARRY()
4837 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), in lowerINTRINSIC_WO_CHAIN()
7223 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0), in combineFP_ROUND()
7287 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0), in combineFP_EXTEND()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp3392 assert(S->getOpcode() == ISD::MERGE_VALUES); in LowerHvxOperationWrapper()
3451 assert(Load->getOpcode() == ISD::MERGE_VALUES); in ReplaceHvxNodeResults()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp739 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
H A DSIISelLowering.cpp5989 if (Res.getOpcode() == ISD::MERGE_VALUES) { in ReplaceNodeResults()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp26664 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, in LowerINTRINSIC_W_CHAIN()
26685 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, in LowerINTRINSIC_W_CHAIN()
26721 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), in LowerINTRINSIC_W_CHAIN()
26762 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), in LowerINTRINSIC_W_CHAIN()
26775 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, in LowerINTRINSIC_W_CHAIN()
27011 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), in LowerINTRINSIC_W_CHAIN()
30765 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), in LowerCMP_SWAP()
31276 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), in lowerAtomicArith()
31283 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), in lowerAtomicArith()
31291 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), in lowerAtomicArith()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1647 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Overflow); in LowerXALUO()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4998 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerSignedALUO()
5059 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerUnsignedALUO()
9908 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry); in LowerUADDSUBO_CARRY()
9982 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, in LowerFSINCOS()
20714 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), in LowerDivRem()
20738 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VT, VT), Values); in LowerDivRem()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11089 return DAG.getNode(ISD::MERGE_VALUES, dl, {MVT::i128, MVT::Other}, in LowerATOMIC_LOAD_STORE()
15070 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other), in expandVSXLoadForLE()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3907 return DAG.getNode(ISD::MERGE_VALUES, DL, VTs, Sum, OutFlag); in lowerADDSUBO_CARRY()
3933 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerXALUO()