Searched refs:MCRegisterClass (Results 1 – 16 of 16) sorted by relevance
66 const MCRegisterClass *GPR32RegClass;67 const MCRegisterClass *GPR64RegClass;68 const MCRegisterClass *FGR32RegClass;69 const MCRegisterClass *FGR64RegClass;70 const MCRegisterClass *AFGR64RegClass;71 const MCRegisterClass *MSA128BRegClass;72 const MCRegisterClass *COP0RegClass;73 const MCRegisterClass *COP2RegClass;74 const MCRegisterClass *COP3RegClass;
35 class MCRegisterClass {141 using regclass_iterator = const MCRegisterClass *;164 const MCRegisterClass *Classes; // Pointer to the regclass array272 unsigned PC, const MCRegisterClass *C, unsigned NC, in InitMCRegisterInfo()379 const MCRegisterClass *RC) const;456 const MCRegisterClass& getRegClass(unsigned i) const { in getRegClass()461 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName()
25 const MCRegisterClass *RC) const { in getMatchingSuperReg()
108 const MCRegisterClass *GPR64RegClass = in hasLiveDefs()
80 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; in isMemOperand()546 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); in clearsSuperRegisters()547 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); in clearsSuperRegisters()548 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); in clearsSuperRegisters()
30 class MCRegisterClass; variable1288 unsigned getRegBitWidth(const MCRegisterClass &RC);
2262 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID); in isSGPR()2568 unsigned getRegBitWidth(const MCRegisterClass &RC) { in getRegBitWidth()
52 const MCRegisterClass *MC;
169 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); in addRegisterFile()
83 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID]; in toDREG()
2693 const MCRegisterClass RC = TRI->getRegClass(RCID); in getRegularReg()4553 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in IsAGPROperand()4593 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign()4594 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in validateVGPRAlign()4713 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateGWS()
756 const MCRegisterClass RC = MRI.getRegClass(RCID); in printRegularOperand()
260 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); in printInst()
3349 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; in addMVEVecListOperands()3350 const MCRegisterClass *RC_out = in addMVEVecListOperands()4483 const MCRegisterClass *RC; in parseRegisterList()4873 const MCRegisterClass *RC = (Spacing == 1) ? in parseVectorList()6852 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias()7309 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
1694 const MCRegisterClass &FPR128RC = in printVectorList()
7797 const MCRegisterClass &WRegClass = in tryParseGPRSeqPair()7799 const MCRegisterClass &XRegClass = in tryParseGPRSeqPair()