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Searched refs:MCInstrDesc (Results 1 – 25 of 206) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h38 class MCInstrDesc; variable
364 const MCInstrDesc &MCID) { in BuildMI()
434 const MCInstrDesc &MCID) { in BuildMI()
444 const MCInstrDesc &MCID) { in BuildMI()
453 const MCInstrDesc &MCID) { in BuildMI()
463 const MCInstrDesc &MCID) { in BuildMI()
471 const MCInstrDesc &MCID) { in BuildMI()
489 const MCInstrDesc &MCID, bool IsIndirect,
496 const MCInstrDesc &MCID, bool IsIndirect,
505 const MCInstrDesc &MCID, bool IsIndirect,
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H A DDFAPacketizer.h45 class MCInstrDesc; variable
103 bool canReserveResources(const MCInstrDesc *MID);
107 void reserveResources(const MCInstrDesc *MID);
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h25 class MCInstrDesc; variable
52 const MCInstrDesc &II,
67 const MCInstrDesc *II,
78 const MCInstrDesc *II,
111 const MCInstrDesc &DbgValDesc,
H A DInstrEmitter.cpp188 const MCInstrDesc &II, in CreateVirtualRegisters()
296 const MCInstrDesc *II, in AddRegisterOperand()
305 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
374 const MCInstrDesc *II, in AddOperand()
635 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
729 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, in AddDbgValueLocationOps()
898 const MCInstrDesc &Desc = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgNoLocation()
924 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValueFromSingleOp()
960 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL); in EmitDbgLabel()
999 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrInfo.h33 const MCInstrDesc *LastDesc; // Raw array to allow static init'n
48 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
63 const MCInstrDesc &get(unsigned Opcode) const { in get()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother()
175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType()
H A DPPCExpandAtomicPseudoInsts.cpp55 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
122 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicRMW128()
123 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicRMW128()
223 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicCmpSwap128()
224 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicCmpSwap128()
H A DPPCFrameLowering.cpp657 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 in emitPrologue()
659 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD in emitPrologue()
661 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU in emitPrologue()
665 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitPrologue()
674 const MCInstrDesc &HashST = in emitPrologue()
1581 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 in emitEpilogue()
1583 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD in emitEpilogue()
1587 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitEpilogue()
1589 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 in emitEpilogue()
1593 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 in emitEpilogue()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrDesc.cpp20 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, in mayAffectControlFlow()
32 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, in hasImplicitDefOfPhysReg()
40 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, in hasDefOfPhysReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h571 ComponentProps(const MCInstrDesc &OpDesc);
714 ComponentInfo(const MCInstrDesc &OpDesc,
735 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY) in InstInfo()
779 VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
1273 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1276 bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1279 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1282 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1341 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) { in getOperandSize()
1428 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.h17 class MCInstrDesc; variable
19 bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp170 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isPredicated()
176 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isCPSRDefined()
186 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, in evaluateBranchTarget()
419 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); in evaluateBranch()
442 evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode_i12()
460 evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode3()
480 evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5()
499 evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5FP16()
540 evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT2_pc()
556 evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT1_s()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp55 bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) { in canReserveResources()
64 void DFAPacketizer::reserveResources(const MCInstrDesc *MID) { in reserveResources()
74 const MCInstrDesc &MID = MI.getDesc(); in canReserveResources()
81 const MCInstrDesc &MID = MI.getDesc(); in reserveResources()
H A DScoreboardHazardRecognizer.cpp122 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType()
177 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h190 static inline unsigned getVLOpNum(const MCInstrDesc &Desc) { in getVLOpNum()
201 static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) { in getSEWOpNum()
210 static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) { in getVecPolicyOpNum()
217 static inline int getFRMOpNum(const MCInstrDesc &Desc) { in getFRMOpNum()
232 static inline int getVXRMOpNum(const MCInstrDesc &Desc) { in getVXRMOpNum()
248 static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) { in isFirstDefTiedToFirstUse()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp161 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
162 SmallVectorImpl<const MCInstrDesc*> &ReplInstrMCID);
219 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst()
220 SmallVectorImpl<const MCInstrDesc*> &InstDescRepl) { in shouldReplaceInst()
276 const MCInstrDesc* OriginalMCID; in shouldExitEarly()
277 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in shouldExitEarly()
355 const MCInstrDesc *MulMCID, *DupMCID; in optimizeVectElement()
421 SmallVector<const MCInstrDesc*, 2> ReplInstrMCID; in optimizeVectElement()
514 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in optimizeLdStInterleave()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ReturnThunks.cpp81 const MCInstrDesc &CS = ST.getInstrInfo()->get(X86::CS_PREFIX); in runOnMachineFunction()
82 const MCInstrDesc &JMP = ST.getInstrInfo()->get(X86::TAILJMPd); in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
H A DM68kInstrInfo.h314 const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const;
317 bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
324 bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h427 const MCInstrDesc &DefMCID,
431 const MCInstrDesc &DefMCID,
435 const MCInstrDesc &UseMCID,
439 const MCInstrDesc &UseMCID,
443 const MCInstrDesc &DefMCID,
445 const MCInstrDesc &UseMCID,
451 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
453 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;
900 const MCInstrDesc &Desc = TII->get(Opcode); in isLegalAddressImm()
H A DMLxExpansionPass.cpp184 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
284 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
339 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
H A DARMHazardRecognizer.cpp31 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
52 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
55 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h24 class MCInstrDesc; variable
100 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp129 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
196 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
376 const MCInstrDesc &MID = MI->getDesc(); in getBaseOpPosition()
398 const MCInstrDesc &MID = MI->getDesc(); in getOffsetOpPosition()
425 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
520 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
702 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
749 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp250 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo()
304 bool AMDGPUCustomBehaviour::isVMEM(const MCInstrDesc &MCID) { in isVMEM()
326 const MCInstrDesc &MCID = MCII.get(Opcode); in isGWS()

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