Searched refs:LowerOp (Results 1 – 3 of 3) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVRegularizer.cpp | 79 auto LowerOp = [&II, &FBegin, &F](Value *V) -> Value * { in runLowerConstExpr() local
107 auto LowerConstantVec = [&II, &LowerOp, &WorkList, in runLowerConstExpr()
118 [LowerOp](Value *V) { return LowerOp(V); }); in runLowerConstExpr()
144 WorkList.push_front(cast<Instruction>(LowerOp(CE))); in runLowerConstExpr()
154 ReplInst = LowerOp(CE); in runLowerConstExpr()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5178 std::string LowerOp = Op.lower(); in parsePKHImm() local
5180 if (ShiftName != LowerOp && ShiftName != UpperOp) in parsePKHImm()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 42549 SDValue LowerOp = SubSrcOps[0]; in combineBitcastvxi1() local
42551 if (LowerOp.getOpcode() == ISD::SETCC && in combineBitcastvxi1()
42554 *DAG.getContext(), LowerOp.getValueType().getVectorMinNumElements()); in combineBitcastvxi1()
42555 if (SDValue V = combineBitcastvxi1(DAG, SubVT, LowerOp, DL, Subtarget)) { in combineBitcastvxi1()
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