| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 924 struct LogicOp { struct
925 LogicOp() = default;
940 case SystemZ::NILMux: return LogicOp(32, 0, 16); in interpretAndImmediate()
941 case SystemZ::NIHMux: return LogicOp(32, 16, 16); in interpretAndImmediate()
942 case SystemZ::NILL64: return LogicOp(64, 0, 16); in interpretAndImmediate()
943 case SystemZ::NILH64: return LogicOp(64, 16, 16); in interpretAndImmediate()
944 case SystemZ::NIHL64: return LogicOp(64, 32, 16); in interpretAndImmediate()
945 case SystemZ::NIHH64: return LogicOp(64, 48, 16); in interpretAndImmediate()
946 case SystemZ::NIFMux: return LogicOp(32, 0, 32); in interpretAndImmediate()
947 case SystemZ::NILF64: return LogicOp(64, 0, 32); in interpretAndImmediate()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2920 SDValue computeLogicOpInGPR(SDValue LogicOp);
3091 SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) { in computeLogicOpInGPR() argument
3092 assert(ISD::isBitwiseLogicOp(LogicOp.getOpcode()) && in computeLogicOpInGPR()
3094 assert(LogicOp.getValueType() == MVT::i1 && in computeLogicOpInGPR()
3096 SDLoc dl(LogicOp); in computeLogicOpInGPR()
3100 bool IsBitwiseNegation = isBitwiseNot(LogicOp); in computeLogicOpInGPR()
3121 LHS = getLogicOperand(LogicOp.getOperand(0)); in computeLogicOpInGPR()
3122 RHS = getLogicOperand(LogicOp.getOperand(1)); in computeLogicOpInGPR()
3139 switch (LogicOp.getOpcode()) { in computeLogicOpInGPR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6150 (LogicOp->getOpcode() == ISD::AND || LogicOp->getOpcode() == ISD::OR) && in foldAndOrOfSETCC()
6154 SDValue LHS = LogicOp->getOperand(0); in foldAndOrOfSETCC()
6155 SDValue RHS = LogicOp->getOperand(1); in foldAndOrOfSETCC()
6174 EVT VT = LogicOp->getValueType(0); in foldAndOrOfSETCC()
6176 SDLoc DL(LogicOp); in foldAndOrOfSETCC()
6892 Z = LogicOp.getOperand(1); in foldLogicOfShifts()
6896 Z = LogicOp.getOperand(0); in foldLogicOfShifts()
9606 SDValue LogicOp = Shift->getOperand(0); in combineShiftOfShiftedLogic() local
9607 if (!LogicOp.hasOneUse()) in combineShiftOfShiftedLogic()
9657 Y = LogicOp.getOperand(1); in combineShiftOfShiftedLogic()
[all …]
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| H A D | TargetLowering.cpp | 4466 unsigned LogicOp = Cond == ISD::SETEQ ? ISD::OR : ISD::AND; in SimplifySetCC() local
4467 return DAG.getNode(LogicOp, dl, VT, IsXZero, IsYZero); in SimplifySetCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1078 isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp,
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| H A D | X86ISelLowering.cpp | 21700 unsigned LogicOp = IsFABS ? X86ISD::FAND : in LowerFABSorFNEG() local
21706 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
21711 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
22299 ISD::NodeType LogicOp = CmpNull ? ISD::OR : ISD::AND; in MatchVectorAllEqualTest() local
22304 if (Op.getOpcode() == LogicOp && matchScalarReduction(Op, LogicOp, VecIns)) { in MatchVectorAllEqualTest()
22322 VecIns.push_back(DAG.getNode(LogicOp, DL, VT, LHS, RHS)); in MatchVectorAllEqualTest()
22336 DAG.matchBinOpReduction(Op.getNode(), BinOp, {LogicOp})) { in MatchVectorAllEqualTest()
56419 const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const { in isDesirableToCombineLogicOpOfSETCC() argument
56421 EVT VT = LogicOp->getValueType(0); in isDesirableToCombineLogicOpOfSETCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 8639 Instruction *LogicOp; in splitBranchCondition() local
8642 m_Br(m_OneUse(m_Instruction(LogicOp)), TBB, FBB))) in splitBranchCondition()
8655 if (match(LogicOp, in splitBranchCondition()
8658 else if (match(LogicOp, m_LogicalOr(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
8685 LogicOp->eraseFromParent(); in splitBranchCondition()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4199 const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const { in isDesirableToCombineLogicOpOfSETCC() argument
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 9354 unsigned LogicOp = (Cond == ISD::SETEQ) ? ISD::AND : ISD::OR; in performOrXorChainCombine() local
9359 Cmp = DAG.getNode(LogicOp, DL, VT, Cmp, CmpChain); in performOrXorChainCombine()
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