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Searched refs:LoadedVT (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1595 EVT LoadedVT = LD->getMemoryVT(); in tryARMIndexedLoad() local
1608 } else if (LoadedVT == MVT::i32 && in tryARMIndexedLoad()
1613 } else if (LoadedVT == MVT::i16 && in tryARMIndexedLoad()
1619 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { in tryARMIndexedLoad()
1670 EVT LoadedVT = LD->getMemoryVT(); in tryT1IndexedLoad() local
1701 EVT LoadedVT = LD->getMemoryVT(); in tryT2IndexedLoad() local
1747 EVT LoadedVT; in tryMVEIndexedLoad() local
1759 LoadedVT = LD->getMemoryVT(); in tryMVEIndexedLoad()
1760 if (!LoadedVT.isVector()) in tryMVEIndexedLoad()
1775 LoadedVT = LD->getMemoryVT(); in tryMVEIndexedLoad()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp883 EVT LoadedVT = LD->getMemoryVT(); in tryLoad() local
890 if (!LoadedVT.isSimple()) in tryLoad()
925 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoad()
934 assert((Isv2x16VT(LoadedVT) || LoadedVT == MVT::v4i8) && in tryLoad()
1028 EVT LoadedVT = MemSD->getMemoryVT(); in tryLoadVector() local
1030 if (!LoadedVT.isSimple()) in tryLoadVector()
1051 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoadVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp76 EVT LoadedVT = LD->getMemoryVT(); in INITIALIZE_PASS() local
83 bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc); in INITIALIZE_PASS()
85 assert(LoadedVT.isSimple()); in INITIALIZE_PASS()
86 switch (LoadedVT.getSimpleVT().SimpleTy) { in INITIALIZE_PASS()
157 assert(LoadedVT.getSizeInBits() <= 32); in INITIALIZE_PASS()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5565 EVT LoadedVT = LD->getMemoryVT(); in Select() local
5585 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5586 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5597 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5598 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5622 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5623 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
5634 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
5636 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp287 EVT LoadedVT = LD->getMemoryVT(); in LegalizeOp() local
288 if (LoadedVT.isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
289 Action = TLI.getLoadExtAction(ExtType, LD->getValueType(0), LoadedVT); in LegalizeOp()
H A DTargetLowering.cpp9462 EVT LoadedVT = LD->getMemoryVT(); in expandUnalignedLoad() local
9467 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); in expandUnalignedLoad()
9468 if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) { in expandUnalignedLoad()
9470 LoadedVT.isVector()) { in expandUnalignedLoad()
9479 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in expandUnalignedLoad()
9480 if (LoadedVT != VT) in expandUnalignedLoad()
9490 unsigned LoadedBytes = LoadedVT.getStoreSize(); in expandUnalignedLoad()
9495 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
9546 LoadedVT); in expandUnalignedLoad()
9552 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && in expandUnalignedLoad()
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H A DDAGCombiner.cpp6421 EVT LoadedVT = LoadN->getMemoryVT(); in isAndLoadExtLoad() local
6423 if (ExtVT == LoadedVT && in isAndLoadExtLoad()
6437 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()