Home
last modified time | relevance | path

Searched refs:LoadVT (Results 1 – 18 of 18) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5658 if (!LoadVT.isVector()) in adjustLoadValueTypeImpl()
5664 EVT FittingLoadVT = LoadVT; in adjustLoadValueTypeImpl()
5704 EVT LoadVT = M->getValueType(0); in adjustLoadValueType() local
5706 EVT EquivLoadVT = LoadVT; in adjustLoadValueType()
5707 if (LoadVT.isVector()) { in adjustLoadValueType()
5765 if (isTypeLegal(LoadVT)) { in lowerIntrinsicLoad()
7539 if ((LoadVT.isVector() && LoadVT.getVectorNumElements() < DMaskLanes) || in lowerImage()
7893 MVT LoadVT = VT.getSimpleVT(); in lowerSBuffer() local
7894 unsigned NumElts = LoadVT.isVector() ? LoadVT.getVectorNumElements() : 1; in lowerSBuffer()
7900 LoadVT = MVT::getVectorVT(LoadVT.getScalarType(), 4); in lowerSBuffer()
[all …]
H A DSIISelLowering.h276 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp765 EVT LoadVT = Ld->getMemoryVT(); in tryIndexedLoad() local
785 if (LoadVT == MVT::i8 && IsPre) in tryIndexedLoad()
787 else if (LoadVT == MVT::i8 && IsPost) in tryIndexedLoad()
789 else if (LoadVT == MVT::i16 && IsPre) in tryIndexedLoad()
791 else if (LoadVT == MVT::i16 && IsPost) in tryIndexedLoad()
793 else if (LoadVT == MVT::i32 && IsPre) in tryIndexedLoad()
795 else if (LoadVT == MVT::i32 && IsPost) in tryIndexedLoad()
797 else if (LoadVT == MVT::i64 && IsPre) in tryIndexedLoad()
799 else if (LoadVT == MVT::i64 && IsPost) in tryIndexedLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp2267 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, in isLoadBitCastBeneficial() argument
2271 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() && in isLoadBitCastBeneficial()
2277 if (!LoadVT.isSimple() || !BitcastVT.isSimple()) in isLoadBitCastBeneficial()
2280 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DStatepointLowering.cpp1272 auto LoadVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitGCRelocate() local
1276 DAG.getLoad(LoadVT, getCurSDLoc(), Chain, SpillSlot, LoadMMO); in visitGCRelocate()
H A DSelectionDAGBuilder.cpp8420 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, in getMemCmpLoad() argument
8428 if (LoadVT.isVector()) in getMemCmpLoad()
8456 Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr, in getMemCmpLoad()
8531 MVT LoadVT; in visitMemCmpBCmpCall() local
8537 LoadVT = MVT::i16; in visitMemCmpBCmpCall()
8540 LoadVT = MVT::i32; in visitMemCmpBCmpCall()
8545 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); in visitMemCmpBCmpCall()
8549 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) in visitMemCmpBCmpCall()
8552 SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this); in visitMemCmpBCmpCall()
8553 SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this); in visitMemCmpBCmpCall()
[all …]
H A DLegalizeDAG.cpp894 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps() local
895 if ((LoadVT.isFloatingPoint() == SrcVT.isFloatingPoint()) && in LegalizeLoadOps()
897 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT))) { in LegalizeLoadOps()
901 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType; in LegalizeLoadOps()
903 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr, in LegalizeLoadOps()
H A DTargetLowering.cpp9313 EVT LoadVT = EVT::getIntegerVT(*DAG.getContext(), NumLoadBits); in scalarizeVectorLoad() local
9320 APInt::getLowBitsSet(NumLoadBits, SrcEltBits), SL, LoadVT); in scalarizeVectorLoad()
9325 DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR, in scalarizeVectorLoad()
9335 LoadVT, SL, /*LegalTypes=*/false); in scalarizeVectorLoad()
9336 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
9338 DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask); in scalarizeVectorLoad()
H A DDAGCombiner.cpp6987 EVT LoadVT = MLoad->getMemoryVT(); in visitAND() local
6989 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) { in visitAND()
6994 LoadVT.getVectorElementType().getScalarSizeInBits(); in visitAND()
6999 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(), in visitAND()
20061 EVT LoadVT; in getStoreMergeCandidates() local
20065 LoadVT = Ld->getMemoryVT(); in getStoreMergeCandidates()
20067 if (MemVT != LoadVT) in getStoreMergeCandidates()
20101 if (LoadVT != OtherLd->getMemoryVT()) in getStoreMergeCandidates()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h609 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
2903 EVT LoadVT = getValueType(DL, Load->getType()); in isExtLoad() local
2907 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) && in isExtLoad()
2920 return isLoadExtLegal(LType, VT, LoadVT); in isExtLoad()
H A DBasicTTIImpl.h1088 EVT LoadVT = EVT::getEVT(Src);
1092 TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3141 EVT LoadVT = EltVT; in LowerFormalArguments() local
3143 LoadVT = MVT::i8; in LowerFormalArguments()
3148 LoadVT = MVT::i32; in LowerFormalArguments()
3150 EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts); in LowerFormalArguments()
3164 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
3170 else if (EltVT != LoadVT) in LowerFormalArguments()
3183 LoadVT.getFixedSizeInBits()) { in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1465 bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
H A DX86ISelLowering.cpp3169 bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, in isLoadBitCastBeneficial() argument
3172 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
3176 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8) in isLoadBitCastBeneficial()
3180 if (LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
3181 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT)) in isLoadBitCastBeneficial()
42968 LoadVT = MVT::getVectorVT(LoadVT, SrcVT.getVectorNumElements()); in combineBitcast()
42970 SDVTList Tys = DAG.getVTList(LoadVT, MVT::Other); in combineBitcast()
52130 MVT LoadVT = MVT::getVectorVT(MemVT, 128 / NumBits); in combineX86INT_TO_FP() local
52131 if (SDValue VZLoad = narrowLoadToVZLoad(LN, MemVT, LoadVT, DAG)) { in combineX86INT_TO_FP()
52159 MVT LoadVT = MVT::getVectorVT(MemVT, 128 / NumBits); in combineCVTP2I_CVTTP2I() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp19466 EVT LoadVT = EVT::getVectorVT( in performExtBinopLoadFold() local
20467 EVT LoadVT = VT; in performLDNT1Combine() local
20469 LoadVT = VT.changeTypeToInteger(); in performLDNT1Combine()
20472 SDValue PassThru = DAG.getConstant(0, DL, LoadVT); in performLDNT1Combine()
20473 SDValue L = DAG.getMaskedLoad(LoadVT, DL, MINode->getChain(), in performLDNT1Combine()
20495 EVT LoadVT = VT; in performLD1ReplicateCombine() local
20497 LoadVT = VT.changeTypeToInteger(); in performLD1ReplicateCombine()
20500 SDValue Load = DAG.getNode(Opcode, DL, {LoadVT, MVT::Other}, Ops); in performLD1ReplicateCombine()
25773 EVT LoadVT = ContainerVT; in LowerFixedLengthVectorLoadToSVE() local
25779 LoadVT = ContainerVT.changeTypeToInteger(); in LowerFixedLengthVectorLoadToSVE()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp7342 EVT LoadVT = N->getValueType(0); in combineBSWAP() local
7343 if (LoadVT == MVT::i16) in combineBSWAP()
7344 LoadVT = MVT::i32; in combineBSWAP()
7347 DAG.getVTList(LoadVT, MVT::Other), in combineBSWAP()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15736 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine() local
15738 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
15739 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp16052 EVT LoadVT = isLaneOp ? VecTy.getVectorElementType() : AlignedVecTy; in TryCombineBaseUpdate() local
16053 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys, Ops, LoadVT, in TryCombineBaseUpdate()
18831 EVT LoadVT = N->getOperand(0).getValueType().getHalfNumVectorElementsVT( in PerformMVEExtCombine() local
18834 LoadVT = LoadVT.getHalfNumVectorElementsVT(*DAG.getContext()); in PerformMVEExtCombine()
18850 VT, Chain, Ptr, MPI, LoadVT, Align(4)); in PerformMVEExtCombine()