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Searched refs:Ld2 (Results 1 – 3 of 3) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp562 auto Ld2 = static_cast<LoadInst*>(PMul0->RHS); in CreateParallelPairs() local
566 if (Ld0 == Ld2 || Ld1 == Ld3) in CreateParallelPairs()
570 if (AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) { in CreateParallelPairs()
574 } else if (AreSequentialLoads(Ld3, Ld2, PMul1->VecLd)) { in CreateParallelPairs()
581 AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) { in CreateParallelPairs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp19346 auto *Ld2 = dyn_cast<LoadSDNode>(SV2->getOperand(1).getOperand(0)); in isLoadOrMultipleLoads() local
19348 if (!Ld0 || !Ld1 || !Ld2 || !Ld3 || !Ld0->isSimple() || !Ld1->isSimple() || in isLoadOrMultipleLoads()
19349 !Ld2->isSimple() || !Ld3->isSimple()) in isLoadOrMultipleLoads()
19353 Loads.push_back(Ld2); in isLoadOrMultipleLoads()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp14857 LoadSDNode *Ld2) -> std::optional<PtrDiff> { in performCONCAT_VECTORSCombine() argument
14861 BaseIndexOffset BIO2 = BaseIndexOffset::match(Ld2, DAG); in performCONCAT_VECTORSCombine()
14867 SDValue P2 = Ld2->getBasePtr(); in performCONCAT_VECTORSCombine()