Searched refs:Ld0 (Results 1 – 2 of 2) sorted by relevance
223 bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);297 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, in AreSequentialLoads() argument299 if (!Ld0 || !Ld1) in AreSequentialLoads()302 if (!LoadPairs.count(Ld0) || LoadPairs[Ld0] != Ld1) in AreSequentialLoads()306 dbgs() << "Ld0:"; Ld0->dump(); in AreSequentialLoads()311 VecMem.push_back(Ld0); in AreSequentialLoads()560 auto Ld0 = static_cast<LoadInst*>(PMul0->LHS); in CreateParallelPairs() local566 if (Ld0 == Ld2 || Ld1 == Ld3) in CreateParallelPairs()569 if (AreSequentialLoads(Ld0, Ld1, PMul0->VecLd)) { in CreateParallelPairs()580 } else if (AreSequentialLoads(Ld1, Ld0, PMul0->VecLd) && in CreateParallelPairs()
19344 auto *Ld0 = dyn_cast<LoadSDNode>(SV2->getOperand(0).getOperand(0)); in isLoadOrMultipleLoads() local19348 if (!Ld0 || !Ld1 || !Ld2 || !Ld3 || !Ld0->isSimple() || !Ld1->isSimple() || in isLoadOrMultipleLoads()19351 Loads.push_back(Ld0); in isLoadOrMultipleLoads()