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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td14 // Latency: #cyc
63 let Latency = Lat;
70 let Latency = Lat;
96 let Latency = 6;
101 let Latency = 6;
106 let Latency = 7;
111 let Latency = 8;
116 let Latency = 9;
120 let Latency = 9;
124 let Latency = 8;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA57WriteRes.td14 // Latency: #cyc
70 let Latency = 6;
75 let Latency = 7;
80 let Latency = 8;
84 let Latency = 9;
88 let Latency = 8;
92 let Latency = 6;
96 let Latency = 6;
100 let Latency = 6;
104 let Latency = 6;
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H A DAArch64SchedKryoDetails.td16 let Latency = 3; let NumMicroOps = 2;
23 let Latency = 3; let NumMicroOps = 2;
30 let Latency = 4; let NumMicroOps = 3;
66 let Latency = 3; let NumMicroOps = 2;
72 let Latency = 3; let NumMicroOps = 2;
78 let Latency = 2; let NumMicroOps = 2;
84 let Latency = 2; let NumMicroOps = 2;
90 let Latency = 2; let NumMicroOps = 2;
96 let Latency = 3; let NumMicroOps = 4;
102 let Latency = 5; let NumMicroOps = 4;
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H A DAArch64SchedKryo.td69 { let Latency = 2; let NumMicroOps = 2; }
71 { let Latency = 2; let NumMicroOps = 2; }
73 { let Latency = 2; let NumMicroOps = 2; }
79 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
80 def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; }
90 { let Latency = 3; let NumMicroOps = 2; }
96 { let Latency = 6; let NumMicroOps = 2; }
104 def : WriteRes<WriteSys, []> { let Latency = 1; }
105 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
106 def : WriteRes<WriteHint, []> { let Latency = 1; }
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H A DAArch64SchedAmpere1.td58 let Latency = 1;
63 let Latency = 1;
68 let Latency = 1;
73 let Latency = 1;
78 let Latency = 1;
83 let Latency = 1;
88 let Latency = 1;
93 let Latency = 2;
98 let Latency = 2;
103 let Latency = 2;
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H A DAArch64SchedExynosM3.td111 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
113 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
209 M3UnitD]> { let Latency = 12;
212 M3UnitD]> { let Latency = 21;
214 def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
215 def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
227 def : WriteRes<WriteLDHi, []> { let Latency = 4;
254 M3UnitFST]> { let Latency = 1;
263 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
264 def : WriteRes<WriteHint, []> { let Latency = 1; }
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H A DAArch64SchedExynosM4.td136 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
139 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
178 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
191 M4UnitL]> { let Latency = 5;
194 M4UnitL]> { let Latency = 5;
198 M4UnitL]> { let Latency = 5;
201 M4UnitL]> { let Latency = 4;
567 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
568 def : WriteRes<WriteHint, []> { let Latency = 1; }
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H A DAArch64SchedExynosM5.td136 def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137 def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
139 def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
196 def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
210 M5UnitL]> { let Latency = 6;
213 M5UnitL]> { let Latency = 6;
217 M5UnitL]> { let Latency = 6;
220 M5UnitL]> { let Latency = 4;
602 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
603 def : WriteRes<WriteHint, []> { let Latency = 1; }
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H A DAArch64SchedAmpere1B.td53 let Latency = 1;
58 let Latency = 1;
63 let Latency = 1;
68 let Latency = 1;
73 let Latency = 1;
78 let Latency = 1;
83 let Latency = 1;
88 let Latency = 1;
93 let Latency = 1;
98 let Latency = 1;
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H A DAArch64SchedA64FX.td95 let Latency = 1;
99 let Latency = 2;
103 let Latency = 4;
107 let Latency = 6;
111 let Latency = 8;
115 let Latency = 9;
119 let Latency = 3;
123 let Latency = 5;
127 let Latency = 4;
131 let Latency = 6;
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H A DAArch64SchedTSV110.td200 let Latency = 1;
206 let Latency = 2;
212 let Latency = 2;
218 let Latency = 2;
224 let Latency = 2;
230 let Latency = 4;
236 let Latency = 4;
242 let Latency = 4;
254 let Latency = 6;
260 let Latency = 6;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleE5500.td52 [5, 2, 2], // Latency = 1
57 [5, 2, 2], // Latency = 1
62 [5, 2, 2, 2], // Latency = 1
68 [6, 2, 2], // Latency = 1 or 2
117 [5, 2, 2], // Latency = 1
141 [5, 2], // Latency = 1
145 [5, 2, 2], // Latency = 1
150 [5, 2], // Latency = 1
154 [5, 2, 2], // Latency = 1
170 [7, 2], // Latency = 3
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H A DPPCScheduleE500mc.td48 [4, 1, 1], // Latency = 1
53 [4, 1, 1], // Latency = 1
75 [11], // Latency = 8
112 [4, 1], // Latency = 1
121 [4, 1], // Latency = 1
133 [6, 1], // Latency = 3
137 [6, 1], // Latency = 3
141 [6, 1], // Latency = 3
146 [6, 1], // Latency = 3
152 [6, 1], // Latency = 3
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H A DPPCScheduleE500.td43 [4, 1, 1], // Latency = 1
48 [4, 1, 1], // Latency = 1
99 [4, 1], // Latency = 1
108 [4, 1], // Latency = 1
120 [6, 1], // Latency = 3
124 [6, 1], // Latency = 3
128 [6, 1], // Latency = 3
133 [6, 1], // Latency = 3
139 [6, 1], // Latency = 3
144 [6, 1], // Latency = 3
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H A DPPCScheduleP10.td86 let Latency = 7;
91 let Latency = 22;
96 let Latency = 24;
101 let Latency = 26;
106 let Latency = 27;
111 let Latency = 36;
116 let Latency = 2;
121 let Latency = 7;
127 let Latency = 13;
264 let Latency = 5;
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H A DPPCScheduleP9.td139 let Latency = 1;
146 let Latency = 1;
153 let Latency = 1;
159 let Latency = 1;
164 let Latency = 1;
170 let Latency = 1;
175 let Latency = 1;
180 let Latency = 1;
185 let Latency = 1;
195 let Latency = 2;
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H A DPPCScheduleP8.td87 // Power8 Instruction Latency & Port Groups:
96 def P8_FX_1C : SchedWriteRes<[P8_FX]> { let Latency = 1; }
97 def P8_FX_2C : SchedWriteRes<[P8_FX]> { let Latency = 2; }
98 def P8_FX_3C : SchedWriteRes<[P8_FX]> { let Latency = 3; }
99 def P8_FX_5C : SchedWriteRes<[P8_FX]> { let Latency = 5; }
104 def P8_BR_2C : SchedWriteRes<[P8_BR]> { let Latency = 2; }
108 def P8_LU_5C : SchedWriteRes<[P8_LU]> { let Latency = 5; }
112 def P8_LS_3C : SchedWriteRes<[P8_LS]> { let Latency = 3; }
125 def P8_XS_2C : SchedWriteRes<[P8_XS]> { let Latency = 2; }
126 def P8_PM_2C : SchedWriteRes<[P8_PM]> { let Latency = 2; }
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedAlderlakeP.td132 let Latency = 11;
146 let Latency = 11;
208 let Latency = 3;
221 let Latency = 3;
248 let Latency = 7;
251 let Latency = 7;
254 let Latency = 8;
264 let Latency = 3;
327 let Latency = 2;
345 let Latency = 3;
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H A DX86SchedSapphireRapids.td131 let Latency = 11;
145 let Latency = 11;
221 let Latency = 3;
231 let Latency = 3;
250 let Latency = 7;
253 let Latency = 7;
256 let Latency = 8;
266 let Latency = 3;
330 let Latency = 2;
348 let Latency = 3;
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H A DX86SchedSkylakeClient.td169 let Latency = 2;
425 let Latency = 2;
430 let Latency = 6;
436 let Latency = 3;
440 let Latency = 2;
549 let Latency = 4;
560 let Latency = 8;
583 let Latency = 6;
629 let Latency = 1;
644 let Latency = 1;
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H A DX86SchedBroadwell.td186 let Latency = 2;
490 let Latency = 2;
495 let Latency = 6;
500 let Latency = 2;
504 let Latency = 2;
566 let Latency = 7;
629 let Latency = 1;
637 let Latency = 1;
645 let Latency = 1;
652 let Latency = 1;
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H A DX86SchedHaswell.td156 let Latency = !add(HWWriteIMulH.Latency, HaswellModel.LoadLatency);
188 let Latency = 2;
489 let Latency = 2;
494 let Latency = 6;
500 let Latency = 2;
504 let Latency = 2;
566 let Latency = 7;
684 let Latency = 7;
743 let Latency = 4;
751 let Latency = 4;
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H A DX86SchedSkylakeServer.td170 let Latency = 2;
426 let Latency = 2;
431 let Latency = 6;
437 let Latency = 3;
441 let Latency = 2;
545 let Latency = 4;
556 let Latency = 8;
579 let Latency = 6;
625 let Latency = 1;
653 let Latency = 1;
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H A DX86SchedIceLake.td177 let Latency = 2;
433 let Latency = 2;
438 let Latency = 6;
444 let Latency = 3;
448 let Latency = 2;
552 let Latency = 4;
563 let Latency = 8;
586 let Latency = 6;
632 let Latency = 1;
660 let Latency = 1;
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H A DX86SchedSandyBridge.td181 let Latency = 2;
454 let Latency = 2;
458 let Latency = 7;
463 let Latency = 3;
467 let Latency = 5;
523 let Latency = 4;
539 let Latency = 7;
561 let Latency = 8;
604 let Latency = 1;
614 let Latency = 1;
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