Searched refs:LaneIndex (Results 1 – 3 of 3) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 343 MachineFunction &MF, int FI, unsigned LaneIndex) { in allocateVirtualVGPRForSGPRSpills() argument
346 if (!LaneIndex) { in allocateVirtualVGPRForSGPRSpills()
354 SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex)); in allocateVirtualVGPRForSGPRSpills()
359 MachineFunction &MF, int FI, unsigned LaneIndex, bool IsPrologEpilog) { in allocatePhysicalVGPRForSGPRSpills() argument
364 if (!LaneIndex) { in allocatePhysicalVGPRForSGPRSpills()
389 SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex)); in allocatePhysicalVGPRForSGPRSpills()
422 unsigned LaneIndex = (NumSpillLanes % WaveSize); in allocateSGPRSpillToVGPRLane() local
425 ? allocatePhysicalVGPRForSGPRSpills(MF, FI, LaneIndex, in allocateSGPRSpillToVGPRLane()
427 : allocateVirtualVGPRForSGPRSpills(MF, FI, LaneIndex); in allocateSGPRSpillToVGPRLane()
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| H A D | SIMachineFunctionInfo.h | 549 unsigned LaneIndex);
551 unsigned LaneIndex,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 846 unsigned LaneIndex; member
2122 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; in isVecListOneDByteIndexed()
2127 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; in isVecListOneDHWordIndexed()
2132 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; in isVecListOneDWordIndexed()
2137 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; in isVecListTwoDByteIndexed()
2142 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; in isVecListTwoDHWordIndexed()
3774 Op->VectorList.LaneIndex = Index; in CreateVectorListIndexed()
4644 const MCExpr *LaneIndex; in parseVectorLane() local
4646 if (getParser().parseExpression(LaneIndex)) in parseVectorLane()
4672 unsigned LaneIndex; in parseVectorList() local
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