| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrShiftRotate.td | 15 /// SHL [~] ASR [~] LSR [~] SWAP [ ]
94 defm LSR : MxSROp<"lsr", srl, MxRODI_R, MxROOP_LS>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 35 LSR, enumerator
56 case AArch64_AM::LSR: return "lsr"; in getShiftExtendName()
77 case 1: return AArch64_AM::LSR; in getShiftType()
105 case AArch64_AM::LSR: STEnc = 1; break; in getShifterImm()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 43 LSR, ///< Logical shift right. enumerator
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| H A D | AVRISelLowering.cpp | 254 NODE(LSR); in getTargetNodeName()
385 Opc8 = AVRISD::LSR; in LowerShifts()
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| /freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | ARMUtils.h | 126 static inline uint32_t LSR(const uint32_t value, const uint32_t amount, in LSR() function
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/ |
| H A D | OrcV2CBindings.cpp | 268 LLVMOrcLookupStateRef LSR = ::wrap(OrcV2CAPIHelper::extractLookupState(LS)); in tryToGenerate() local
288 auto Err = unwrap(TryToGenerate(::wrap(this), Ctx, &LSR, CLookupKind, in tryToGenerate()
293 OrcV2CAPIHelper::resetLookupState(LS, ::unwrap(LSR)); in tryToGenerate()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedA510.td | 678 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
679 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
680 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
681 "^(ASR|LSL|LSR)_ZPZI_[BHSD]",
682 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
683 "^(ASR|LSL|LSR)_ZPZZ_[BHSD]",
684 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
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| H A D | AArch64SchedNeoverseV1.td | 525 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
532 // Arithmetic, flagset, LSR/ASR/ROR shift or LSL shift > 4
1390 (instregex "^(ASR|LSL|LSR)_WIDE_Z(Pm|Z)Z_[BHS]",
1391 "^(ASR|LSL|LSR)_ZPm[IZ]_[BHSD]",
1392 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
1393 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
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| H A D | AArch64SchedPredicates.td | 55 def CheckShiftLSR : CheckImmOperand_s<3, "AArch64_AM::LSR">;
|
| H A D | AArch64SchedNeoverseN2.td | 653 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
1623 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]$",
1624 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]$",
1625 "^(ASR|LSL|LSR)_ZPmI_[BHSD]$",
1626 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]$",
1627 "^(ASR|LSL|LSR)_ZZI_[BHSD]$",
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| H A D | AArch64SchedNeoverseV2.td | 1121 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
2132 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]",
2133 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]",
2134 "^(ASR|LSL|LSR)_ZPmI_[BHSD]",
2135 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]",
2136 "^(ASR|LSL|LSR)_ZZI_[BHSD]",
2137 "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]",
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| H A D | AArch64AsmPrinter.cpp | 635 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)), in emitHwasanMemaccessSymbols()
725 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)), in emitHwasanMemaccessSymbols()
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| H A D | AArch64ISelDAGToDAG.cpp | 643 return AArch64_AM::LSR; in getShiftTypeForNode()
2705 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) { in getUsefulBitsFromOrWithShiftedReg()
3240 EncodedShiftImm = AArch64_AM::getShifterImm(AArch64_AM::LSR, SrlImm); in isWorthFoldingIntoOrrWithShift()
3340 AArch64_AM::getShifterImm(AArch64_AM::LSR, SrlImm), DL, VT)}; in tryOrrWithShift()
3503 SDNode *LSR = CurDAG->getMachineNode( in tryBitfieldInsertOpFromOr() local
3512 SDValue Ops[] = {Dst, SDValue(LSR, 0), in tryBitfieldInsertOpFromOr()
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| H A D | AArch64SchedAmpere1.td | 994 (instregex "(ASR|LSL|LSR|ROR)V(W|X)r")>;
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| H A D | AArch64SchedAmpere1B.td | 976 (instregex "(ASR|LSL|LSR|ROR)V(W|X)r")>;
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| H A D | AArch64SchedNeoverseN1.td | 310 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 599 LSR, enumerator
|
| /freebsd-14.2/sys/crypto/openssl/arm/ |
| H A D | bsaes-armv7.S | 567 .LSR: label
921 vldmia r6, {q12} @ .LSR
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2707 LatticeCell LSR; in evaluateHexCondMove() local
2708 if (!evaluate(R, LR, LSR)) in evaluateHexCondMove()
2710 RC.meet(LSR); in evaluateHexCondMove()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM7.td | 338 def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)")>;
|
| H A D | ARMInstrThumb.td | 1180 // LSR immediate
1191 // LSR register
|
| H A D | ARMScheduleR52.td | 330 (instregex "ASRr", "RORS?r", "LSR", "LSL")>;
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| H A D | ARMScheduleM85.td | 439 (instregex "(t|t2)(LSL|LSR|ASR|ROR|SBFX|UBFX)", "t2MOVsr(a|l)")>;
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1474 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1576 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1587 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isLogicalShifter()
3563 .Case("lsr", AArch64_AM::LSR) in tryParseOptionalShiftExtend()
3586 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.td | 303 defm LSR : ArcBinaryEXT5Inst<0b000001, "lsr">;
|