| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 81 DAG_FUNCTION(lrint, 1, 1, experimental_constrained_lrint, LRINT)
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 959 LRINT, enumerator
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| H A D | BasicTTIImpl.h | 1941 ISD = ISD::LRINT; in getTypeBasedIntrinsicInstrCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 886 ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT}, in initActions()
938 ISD::LLROUND, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN}, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 387 case ISD::LRINT: return "lrint"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 104 case ISD::LRINT: in ScalarizeVectorResult()
686 case ISD::LRINT: in ScalarizeVectorOperand()
1104 case ISD::LRINT: in SplitVectorResult()
3038 case ISD::LRINT: in SplitVectorOperand()
4264 case ISD::LRINT: in WidenVectorResult()
6056 case ISD::LRINT: in WidenVectorOperand()
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| H A D | LegalizeFloatTypes.cpp | 935 case ISD::LRINT: Res = SoftenFloatOp_LRINT(N); break; in SoftenFloatOperand()
1905 case ISD::LRINT: Res = ExpandFloatOp_LRINT(N); break; in ExpandFloatOperand()
2234 case ISD::LRINT: in PromoteFloatOperand()
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| H A D | LegalizeVectorOps.cpp | 407 case ISD::LRINT: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 306 case ISD::LRINT: in PromoteIntegerResult()
2644 case ISD::LRINT: in ExpandIntegerResult()
3806 } else if (N->getOpcode() == ISD::LRINT || in ExpandIntRes_XROUND_XRINT()
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| H A D | LegalizeDAG.cpp | 1030 case ISD::LRINT: in LegalizeOp()
4586 case ISD::LRINT: in ConvertNodeToLibcall()
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| H A D | SelectionDAGBuilder.cpp | 6517 case Intrinsic::lrint: Opcode = ISD::LRINT; break; in visitIntrinsicCall()
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| H A D | SelectionDAG.cpp | 5144 case ISD::LRINT: in isKnownNeverNaN()
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| H A D | DAGCombiner.cpp | 2021 case ISD::LRINT: in visit()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 527 def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 421 ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT, in RISCVTargetLowering()
816 setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); in RISCVTargetLowering()
6359 case ISD::LRINT: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 556 setOperationAction(ISD::LRINT, MVT::f64, Legal); in PPCTargetLowering()
557 setOperationAction(ISD::LRINT, MVT::f32, Legal); in PPCTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 277 setOperationAction(ISD::LRINT, MVT::f32, Custom); in X86TargetLowering()
278 setOperationAction(ISD::LRINT, MVT::f64, Custom); in X86TargetLowering()
283 setOperationAction(ISD::LRINT, MVT::i64, Custom); in X86TargetLowering()
796 setOperationAction(ISD::LRINT, MVT::f80, Custom); in X86TargetLowering()
31921 case ISD::LRINT: in LowerOperation()
32616 case ISD::LRINT: in ReplaceNodeResults()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 715 for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in AArch64TargetLowering()
772 ISD::LLROUND, ISD::LRINT, ISD::LLRINT, in AArch64TargetLowering()
6388 case ISD::LRINT: in LowerOperation()
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