| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1322 if (!matchIsNotNaN(PredL, LHS0, LHS1) || in matchIsFiniteTest()
1340 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1360 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1372 return getFCmpValue(NewPred, LHS0, LHS1, Builder); in foldLogicOfFCmps()
3161 match(LHS1, m_APInt(LHSC)); in foldAndOrOfICmps()
3167 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldAndOrOfICmps()
3169 std::swap(LHS0, LHS1); in foldAndOrOfICmps()
3171 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldAndOrOfICmps()
3980 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldXorOfICmps()
3981 std::swap(LHS0, LHS1); in foldXorOfICmps()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LICM.cpp | 2428 Value *LHS1, *LHS2, *RHS1, *RHS2; in hoistMinMax() local
2429 if (!MatchICmpAgainstInvariant(Cond1, P1, LHS1, RHS1) || in hoistMinMax()
2432 if (P1 != P2 || LHS1 != LHS2) in hoistMinMax()
2460 Value *NewCond = Builder.CreateICmp(P, LHS1, NewRHS); in hoistMinMax()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1851 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in simplifyAndOrOfFCmps() local
1870 if (((LHS1 == RHS0 || LHS1 == RHS1) && in simplifyAndOrOfFCmps()
1873 isKnownNeverNaN(LHS1, DL, TLI, 0, Q.AC, Q.CxtI, Q.DT))) in simplifyAndOrOfFCmps()
1884 if (((RHS1 == LHS0 || RHS1 == LHS1) && in simplifyAndOrOfFCmps()
1886 ((RHS0 == LHS0 || RHS0 == LHS1) && in simplifyAndOrOfFCmps()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 829 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, in getAVRCmp() local
857 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); in getAVRCmp()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1011 auto *LHS1 = dyn_cast<ConstantSDNode>(LHS.getOperand(1)); in isDesirableToCommuteWithShift() local
1012 return LHS0 && LHS1 && RHSLd && LHS0->getExtensionType() == ISD::ZEXTLOAD && in isDesirableToCommuteWithShift()
1013 LHS1->getAPIntValue() == LHS0->getMemoryVT().getScalarSizeInBits() && in isDesirableToCommuteWithShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6166 SDValue LHS1 = LHS->getOperand(1); in foldAndOrOfSETCC() local
6170 auto *LHS1C = isConstOrConstSplat(LHS1); in foldAndOrOfSETCC()
6208 Operand1 = LHS1; in foldAndOrOfSETCC()
6211 } else if (LHS1 == RHS1) { in foldAndOrOfSETCC()
6212 CommonValue = LHS1; in foldAndOrOfSETCC()
6221 Operand1 = LHS1; in foldAndOrOfSETCC()
6224 } else if (RHS0 == LHS1) { in foldAndOrOfSETCC()
6225 CommonValue = LHS1; in foldAndOrOfSETCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5678 SDValue LHS1, LHS2; in OptimizeVFPBrcond() local
5680 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
5687 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
12216 Register LHS1 = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
12220 .addReg(LHS1) in EmitInstrWithCustomInserter()
12230 .addReg(LHS1) in EmitInstrWithCustomInserter()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22935 SDValue LHS1, LHS2; in splitIntVSETCC() local
22936 std::tie(LHS1, LHS2) = splitVector(LHS, DAG, dl); in splitIntVSETCC()
22946 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC), in splitIntVSETCC()
47458 SDValue LHS1 = LHS.getOperand(1); in combineVectorHADDSUB() local
47461 if ((LHS0 == LHS1 || LHS0.isUndef() || LHS1.isUndef()) && in combineVectorHADDSUB()
47465 LHS0.isUndef() ? LHS1 : LHS0, in combineVectorHADDSUB()
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