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Searched refs:LD1 (Results 1 – 13 of 13) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td3082 // We must do vector loads with LD1 in big-endian.
3096 // We must do vector loads with LD1 in big-endian.
3230 // We must use LD1 to perform vector loads in big-endian.
3251 // We must use LD1 to perform vector loads in big-endian.
7823 defm LD1 : SIMDLd1Multiple<"ld1">;
7939 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
7950 // Generate LD1 for extload if memory type does not match the
7955 // In this case, the index must be adjusted to match LD1 type.
7959 Instruction LD1, SDNodeXForm IdxOp>
8022 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
[all …]
H A DAArch64SchedKryoDetails.td1017 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)$")>;
1023 (instregex "LD1(i8|i16|i32)$")>;
1035 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)_POST$")>;
1041 (instregex "LD1(i8|i16|i32)_POST$")>;
H A DAArch64SchedNeoverseV1.td1108 (instregex "^LD1(i|Rv)(8|16|32|64)$",
1691 def : InstRW<[V1Write_6c_1L01], (instregex "^LD1[BHWD]_IMM$",
1695 "^LD1[BWD]$",
H A DAArch64SchedFalkorDetails.td781 def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|…
783 … (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))_POST$")>;
H A DAArch64SchedA510.td1171 def : InstRW<[CortexA510Write<3, CortexA510UnitLd>], (instregex "^LD1[BHWD]_IMM$",
1176 def : InstRW<[CortexA510Write<3, CortexA510UnitLd>], (instregex "^LD1[BHWD]$",
H A DAArch64SchedNeoverseN2.td2085 def : InstRW<[N2Write_6cyc_1L], (instregex "^LD1[BHWD]_IMM$",
2090 def : InstRW<[N2Write_6cyc_1L01], (instregex "^LD1[BHWD]$",
H A DAArch64SchedNeoverseN1.td845 (instregex "LD1(i|Rv)(8|16|32|64)$",
H A DAArch64SchedNeoverseV2.td2612 def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]_IMM$",
2617 def : InstRW<[V2Write_6cyc_1L], (instregex "^LD1[BHWD]$",
H A DAArch64InstrFormats.td10580 // LD1 instructions have extra "1d" variants.
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp15021 auto *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); in CombineConsecutiveLoads() local
15028 std::swap(LD1, LD2); in CombineConsecutiveLoads()
15030 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !ISD::isNON_EXTLoad(LD2) || in CombineConsecutiveLoads()
15031 !LD1->hasOneUse() || !LD2->hasOneUse() || in CombineConsecutiveLoads()
15032 LD1->getAddressSpace() != LD2->getAddressSpace()) in CombineConsecutiveLoads()
15036 EVT LD1VT = LD1->getValueType(0); in CombineConsecutiveLoads()
15039 DAG.areNonVolatileConsecutiveLoads(LD2, LD1, LD1Bytes, 1) && in CombineConsecutiveLoads()
15041 *LD1->getMemOperand(), &LD1Fast) && LD1Fast) in CombineConsecutiveLoads()
15042 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(), LD1->getBasePtr(), in CombineConsecutiveLoads()
15043 LD1->getPointerInfo(), LD1->getAlign()); in CombineConsecutiveLoads()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_neon.td721 def LD1 : WInst<"vld1", ".(c*!)", "dQdPlQPl">;
H A Darm_sve.td2019 defm LD1 : MultiVecLoad<"ld1">;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14586 LoadSDNode *LD1 = cast<LoadSDNode>(PreviousInput); in combineBVOfConsecutiveLoads() local
14595 if (!DAG.areNonVolatileConsecutiveLoads(LD2, LD1, ElemSize, 1)) in combineBVOfConsecutiveLoads()
14597 if (!DAG.areNonVolatileConsecutiveLoads(LD1, LD2, ElemSize, 1)) in combineBVOfConsecutiveLoads()