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Searched refs:JALR (Results 1 – 25 of 27) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp213 if (Inst.getOpcode() == RISCV::JALR) { in evaluateBranch()
233 case RISCV::JALR: in isTerminator()
246 case RISCV::JALR: in isCall()
258 case RISCV::JALR: in isReturn()
287 case RISCV::JALR: in isIndirectBranch()
307 case RISCV::JALR: in isBranchImpl()
H A DRISCVMCCodeEmitter.cpp153 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
156 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
175 MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm); in expandTLSDESCCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp59 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
89 case Mips::JALR: in isCall()
H A DMipsInstPrinter.cpp306 case Mips::JALR: in printAlias()
/freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h112 I_TYPE_INST(JALR);
276 LUI, AUIPC, JAL, JALR, B, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI,
H A DRISCVCInstructions.h128 return JALR{Rd{0}, rs1, 0}; in DecodeC_JR()
135 return JALR{Rd{1}, rs1, 0}; in DecodeC_JALR()
H A DEmulateInstructionRISCV.cpp427 {"JALR", 0x707F, 0x67, DecodeIType<JALR>},
683 bool operator()(JALR inst) { in operator ()()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td616 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
931 def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0), 3>;
932 def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12:$offset)>;
933 def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>;
934 def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>;
935 def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>;
936 def : InstAlias<"ret", (JALR X0, X1, 0), 4>;
1626 PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
1663 PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
1667 PseudoInstExpansion<(JALR X0, X1, 0)>;
[all …]
H A DRISCVInstrInfoC.td996 def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),
1008 def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),
H A DRISCVAsmPrinter.cpp629 OutStreamer->emitInstruction(MCInstBuilder(RISCV::JALR) in EmitHwasanMemaccessSymbols()
H A DRISCVInstrFormats.td153 def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>;
H A DRISCVRegisterInfo.td152 // Don't use X1 or X5 for JALR since that is a hint to pop the return address
/freebsd-14.2/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp64 JALR = 0x67, enumerator
242 write32le(buf + 28, itype(JALR, 0, X_T3, 0)); in writePltHeader()
254 write32le(buf + 8, itype(JALR, X_T1, X_T3, 0)); in writePlt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A DELF_riscv.cpp594 const auto JALR = in relaxCall() local
596 const auto RD = extractBits(JALR, 7, 5); in relaxCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips32r6InstrInfo.td1001 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>,
1130 def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6;
1131 def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO,
H A DMipsDelaySlotFiller.cpp587 case Mips::JALR: in getEquivalentCallShort()
H A DMipsInstrInfo.cpp883 case Mips::JALR: in verifyInstruction()
H A DMipsAsmPrinter.cpp126 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td2256 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM, ISA_MIPS1;
2257 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>, ISA_MIPS1;
2281 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
2301 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
2689 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
3163 // (JALR GPR32:$dst)>;
H A DMipsSEISelDAGToDAG.cpp194 case Mips::JALR: in processFunctionAfterISel()
H A DMipsScheduleP5600.td83 def : InstRW<[P5600WriteJumpAndLink], (instrs JAL, JALR, JALRHBPseudo,
H A DMipsFastISel.cpp1553 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::JALR), in fastLowerCall()
H A DMips64InstrInfo.td279 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>,
H A DMipsScheduleGeneric.td298 def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZAL, JAL, JALR, JALR_HB,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2131 JalrInst.setOpcode(Mips::JALR); in processInstruction()
2718 JalrInst.setOpcode(Mips::JALR); in expandJalWithRegs()
2727 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR); in expandJalWithRegs()

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