Searched refs:IsWave32 (Results 1 – 10 of 10) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 89 const bool IsWave32 = ST.isWave32(); in optimizeVccBranch() local 91 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in optimizeVccBranch() 92 const unsigned And = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in optimizeVccBranch() 93 const unsigned AndN2 = IsWave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64; in optimizeVccBranch() 94 const unsigned Mov = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in optimizeVccBranch()
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| H A D | SILowerI1Copies.h | 43 bool IsWave32 = false;
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| H A D | SILowerControlFlow.cpp | 716 bool IsWave32 = ST.isWave32(); in lowerInitExec() local 721 TII->get(IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), Exec) in lowerInitExec() 770 TII->get(IsWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64), Exec) in lowerInitExec() 780 TII->get(IsWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64), in lowerInitExec()
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| H A D | SIFixSGPRCopies.cpp | 1098 bool IsWave32 = MF.getSubtarget<GCNSubtarget>().isWave32(); in fixSCCCopies() local 1115 TII->get(IsWave32 ? AMDGPU::S_CSELECT_B32 in fixSCCCopies() 1127 unsigned Opcode = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in fixSCCCopies() 1128 Register Exec = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in fixSCCCopies()
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| H A D | SIRegisterInfo.cpp | 107 bool IsWave32; member 113 bool IsWave32, MachineBasicBlock::iterator MI, int Index, in SGPRSpillBuilder() 115 : SGPRSpillBuilder(TRI, TII, IsWave32, MI, MI->getOperand(0).getReg(), in SGPRSpillBuilder() 119 bool IsWave32, MachineBasicBlock::iterator MI, Register Reg, in SGPRSpillBuilder() 124 IsWave32(IsWave32) { in SGPRSpillBuilder() 129 if (IsWave32) { in SGPRSpillBuilder() 146 Data.PerVGPR = IsWave32 ? 32 : 64; in getPerVGPRData() 201 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass; in prepare()
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| H A D | SILowerI1Copies.cpp | 516 IsWave32 = ST->isWave32(); in PhiLoweringHelper() 518 if (IsWave32) { in PhiLoweringHelper()
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| H A D | AMDGPUInstructionSelector.cpp | 1419 const bool IsWave32 = (STI.getWavefrontSize() == 32); in selectBallot() local 1423 if (Size != STI.getWavefrontSize() && (!Is64 || !IsWave32)) in selectBallot() 1452 BuildCopy(IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC); in selectBallot()
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| H A D | SIInstrInfo.cpp | 5383 bool IsWave32 = ST.isWave32(); in insertScratchExecCopy() local 5388 unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in insertScratchExecCopy() 5389 MCRegister Exec = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in insertScratchExecCopy() 5399 IsWave32 ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64; in insertScratchExecCopy()
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| H A D | SIISelLowering.cpp | 4649 bool IsWave32 = ST.isWave32(); in lowerWaveReduce() local 4650 unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerWaveReduce() 4651 unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in lowerWaveReduce() 4675 unsigned SFFOpc = IsWave32 ? AMDGPU::S_FF1_I32_B32 : AMDGPU::S_FF1_I32_B64; in lowerWaveReduce() 4688 IsWave32 ? AMDGPU::S_BITSET0_B32 : AMDGPU::S_BITSET0_B64; in lowerWaveReduce() 4701 unsigned CMPOpc = IsWave32 ? AMDGPU::S_CMP_LG_U32 : AMDGPU::S_CMP_LG_U64; in lowerWaveReduce()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 1041 bool IsWave32 = EnableWavefrontSize32 ? in getVGPRAllocGranule() local 1046 return IsWave32 ? 24 : 12; in getVGPRAllocGranule() 1049 return IsWave32 ? 16 : 8; in getVGPRAllocGranule() 1051 return IsWave32 ? 8 : 4; in getVGPRAllocGranule() 1059 bool IsWave32 = EnableWavefrontSize32 ? in getVGPREncodingGranule() local 1063 return IsWave32 ? 8 : 4; in getVGPREncodingGranule() 1071 bool IsWave32 = STI->getFeatureBits().test(FeatureWavefrontSize32); in getTotalNumVGPRs() local 1073 return IsWave32 ? 1536 : 768; in getTotalNumVGPRs() 1074 return IsWave32 ? 1024 : 512; in getTotalNumVGPRs()
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