Searched refs:IsVGPR (Results 1 – 5 of 5) sorted by relevance
554 bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR; in getMachineOpValue() local555 Op = Idx | (IsVGPR << 8); in getMachineOpValue()569 bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR; in getMachineOpValueT16() local570 Op = Idx | (IsVGPR << 8); in getMachineOpValueT16()617 bool IsVGPR = Encoding & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR; in getMachineOpValueT16Lo128() local618 assert((!IsVGPR || isUInt<7>(RegIdx)) && "VGPR0-VGPR127 expected!"); in getMachineOpValueT16Lo128()619 Op = (IsVGPR ? 0x100 : 0) | (IsHi ? 0x80 : 0) | RegIdx; in getMachineOpValueT16Lo128()
315 bool IsVGPR = Imm & (1 << 8); in decodeOperand_VSrcT16_Lo128() local316 if (IsVGPR) { in decodeOperand_VSrcT16_Lo128()331 bool IsVGPR = Imm & (1 << 8); in decodeOperand_VSrcT16() local332 if (IsVGPR) { in decodeOperand_VSrcT16()
2940 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID; in selectG_GLOBAL_VALUE() local2941 I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32)); in selectG_GLOBAL_VALUE()2942 if (IsVGPR) in selectG_GLOBAL_VALUE()2946 DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI); in selectG_GLOBAL_VALUE()2961 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID; in selectG_PTRMASK() local2974 if (!IsVGPR && Ty.getSizeInBits() == 64 && in selectG_PTRMASK()2984 unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32; in selectG_PTRMASK()2986 = IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass; in selectG_PTRMASK()3006 if (!IsVGPR) in selectG_PTRMASK()
1223 bool IsVGPR = TRI->isVGPR(MRI, Reg); in spillVGPRtoAGPR() local1225 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()1235 unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 in spillVGPRtoAGPR()
1804 const bool IsVGPR = TRI->isVectorRegister(*MRI, Op.getReg()); in generateWaitcntInstBefore() local1806 if (IsVGPR) { in generateWaitcntInstBefore()