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Searched refs:IsStore (Results 1 – 25 of 31) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp158 bool IsStore = false; in emitInstruction() local
160 &IsStore); in emitInstruction()
166 bool MaskAfter = IsSPFirstOperand && !IsStore; in emitInstruction()
211 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
212 if (IsStore) in isBasePlusOffsetMemoryAccess()
213 *IsStore = false; in isBasePlusOffsetMemoryAccess()
243 if (IsStore) in isBasePlusOffsetMemoryAccess()
244 *IsStore = true; in isBasePlusOffsetMemoryAccess()
251 if (IsStore) in isBasePlusOffsetMemoryAccess()
252 *IsStore = true; in isBasePlusOffsetMemoryAccess()
H A DMipsMCNaCl.h21 bool *IsStore = nullptr);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp75 unsigned int IsStore : 1; member
367 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
373 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
683 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
700 !SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
705 if (SwapVector[UseOfUseIdx].IsStore) { in recordUnoptimizableWebs()
722 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
730 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
796 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
1008 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kCollapseMOVEMPass.cpp205 bool IsStore = false) { in ProcessMI() argument
210 if (State.isStore() == IsStore && State.getBase() == Reg && in ProcessMI()
219 return ProcessMI(MBB, MI, State, Mask, Offset, Reg, IsStore); in ProcessMI()
228 IsStore ? State.setStore() : State.setLoad(); in ProcessMI()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td36 bit IsStore = false;
52 let TSFlags{6...6} = IsStore;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp405 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
412 if (IsStore && MI->mayLoad()) in canHoistLoadStoreTo()
454 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
464 if (IsStore) { in changeToAddrMode()
471 if (IsStore) in changeToAddrMode()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td871 bit IsStore = ?;
1197 let IsStore = true;
1202 let IsStore = true;
1209 let IsStore = true;
1214 let IsStore = true;
1220 let IsStore = true;
1226 let IsStore = true;
1232 let IsStore = true;
1238 let IsStore = true;
1243 let IsStore = true;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp1217 bool IsStore = MI->mayStore(); in spillVGPRtoAGPR() local
1221 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1222 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1254 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
1257 int LoadStoreOp = IsStore ? in buildMUBUFOffsetLoadStore()
1286 bool IsStore = TII->get(LoadStoreOp).mayStore(); in getFlatScratchSpillOpcode() local
1293 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in getFlatScratchSpillOpcode()
1333 bool IsStore = Desc->mayStore(); in buildSpillLoadStore() local
1539 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
1611 if (IsStore) { in buildSpillLoadStore()
[all …]
H A DAMDGPUInstructions.td457 let IsStore = 1;
541 let IsStore = 1, AddressSpaces = !cast<AddressSpaceList>("StoreAddress_"#as).AddrSpaces in {
565 } // End let IsStore = 1, AddressSpaces = ...
702 let IsStore = 1;
707 let IsStore = 1;
H A DSIInstrInfo.td462 let IsStore = 1;
468 let IsStore = 1;
474 let IsStore = 1;
480 let IsStore = 1;
487 let IsStore = 1;
504 let IsStore = 1;
510 let IsStore = 1;
530 let IsStore = 1;
536 let IsStore = 1;
601 let IsStore = 1;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp156 const bool IsStore = GenericOpc == TargetOpcode::G_STORE; in selectLoadStoreOp() local
161 return IsStore ? PPC::STW : PPC::LWZ; in selectLoadStoreOp()
163 return IsStore ? PPC::STD : PPC::LD; in selectLoadStoreOp()
171 return IsStore ? PPC::STFS : PPC::LFS; in selectLoadStoreOp()
173 return IsStore ? PPC::STFD : PPC::LFD; in selectLoadStoreOp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.cpp339 bool IsStore = MI.getOperand(0).isReg() && MI.getOperand(1).isReg(); in optimizeMOV() local
340 unsigned AddrBase = IsStore; in optimizeMOV()
341 unsigned RegOp = IsStore ? 0 : 5; in optimizeMOV()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp464 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
465 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
466 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
483 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
H A DARMLoadStoreOptimizer.cpp502 bool IsStore = in UpdateBaseRegUses() local
505 if (IsLoad || IsStore) { in UpdateBaseRegUses()
518 if (Offset >= 0 && !(IsStore && InstrSrcReg == Base)) in UpdateBaseRegUses()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_sve.td337 def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore, IsStreamingCompatible], M…
338 def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore, IsStreamingCompatible], M…
339 def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore, IsStreamingCompatible], M…
340 def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore, IsStreamingCompatible], M…
341 def SVST1H_U : MInst<"svst1h[_{d}]", "vPFd", "UiUl", [IsStore, IsStreamingCompatible], M…
355 …def SVST1_BF : MInst<"svst1[_{d}]", "vPpd", "b", [IsStore, IsStreamingCompatible], MemE…
356 …def SVST1_VNUM_BF : MInst<"svst1_vnum[_{d}]", "vPpld", "b", [IsStore, IsStreamingCompatible], MemE…
457 …def SVST1UWQ : MInst<"svst1wq[_{d}]", "vPcd", "iUif", [IsStore], MemEltTyInt32, "aarch64_sve…
458 …def SVST1UWQ_VNUM : MInst<"svst1wq_vnum[_{d}]", "vPcld", "iUif", [IsStore], MemEltTyInt32, "aarch6…
460 …def SVST1UDQ : MInst<"svst1dq[_{d}]", "vPcd", "lUld", [IsStore], MemEltTyInt64, "aarch64_sve…
[all …]
H A DTargetBuiltins.h286 bool isStore() const { return Flags & IsStore; } in isStore()
H A Darm_sme.td63 [IsStore, IsOverloadNone, IsStreaming, IsInZA],
67 [IsStore, IsOverloadNone, IsStreaming, IsInZA],
71 [IsStore, IsOverloadNone, IsStreaming, IsInZA],
75 [IsStore, IsOverloadNone, IsStreaming, IsInZA],
H A Darm_sve_sme_incl.td199 def IsStore : FlagType<0x00004000>;
/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/
H A DCGAtomic.cpp1449 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
1476 if (IsStore) in EmitAtomicExpr()
1488 if (IsLoad || IsStore) in EmitAtomicExpr()
1512 if (!IsStore) in EmitAtomicExpr()
1516 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1533 if (!IsStore) { in EmitAtomicExpr()
1551 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp212 bool IsStore = TID.mayStore(); in printTH() local
232 if (!IsStore && TH == AMDGPU::CPol::TH_RESERVED) in printTH()
238 O << (IsStore ? "TH_STORE_" : "TH_LOAD_"); in printTH()
248 : (IsStore ? "RT_WB" : "LU")); in printTH()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp845 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
846 if (!IsLoad && !IsStore) in canMoveMemTo()
867 bool Conflict = (L && IsStore) || S; in canMoveMemTo()
H A DHexagonConstExtenders.cpp1148 bool IsStore = MI.mayStore(); in recordExtender() local
1157 if (IsLoad || IsStore) { in recordExtender()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp1374 bool IsStore) { in getCombinedCountBitMask() argument
1377 if (IsStore) { in getCombinedCountBitMask()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp21780 bool IsStore = false; in performNEONPostLDSTCombine() local
21795 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
21797 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
21799 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
21807 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
21809 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
21811 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
21825 NumVecs = 2; IsStore = true; IsLaneOp = true; break; in performNEONPostLDSTCombine()
21833 if (IsStore) in performNEONPostLDSTCombine()
21852 if (IsLaneOp || IsStore) in performNEONPostLDSTCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp4937 bool IsStore = (Instruction::Store == Opcode); in getMaskedMemoryOpCost() local
4948 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { in getMaskedMemoryOpCost()
4959 SrcVTy, DemandedElts, IsLoad, IsStore, CostKind); in getMaskedMemoryOpCost()

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