| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 657 bool IsSignaling = false) const;
660 bool IsSignaling) const;
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| H A D | SystemZISelLowering.cpp | 3036 bool IsSignaling = false) { in getCmp() argument
3057 else if (!IsSignaling) in getCmp()
3307 bool IsSignaling) const { in lowerVectorSETCC()
3310 assert (!IsSignaling || Chain); in lowerVectorSETCC()
3311 CmpMode Mode = IsSignaling ? CmpMode::SignalingFP : in lowerVectorSETCC()
3396 bool IsSignaling) const { in lowerSTRICT_FSETCC()
3405 Chain, IsSignaling); in lowerSTRICT_FSETCC()
3409 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL, Chain, IsSignaling)); in lowerSTRICT_FSETCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/IR/ |
| H A D | IRBuilder.cpp | 1057 MDNode *FPMathTag, bool IsSignaling) { in CreateFCmpHelper() argument
1059 auto ID = IsSignaling ? Intrinsic::experimental_constrained_fcmps in CreateFCmpHelper()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 1936 bool IsSignaling) { in FloatExpandSetCCOperands() argument
1950 RHSHi, ISD::SETOEQ, Chain, IsSignaling); in FloatExpandSetCCOperands()
1953 RHSLo, CCCode, OutputChain, IsSignaling); in FloatExpandSetCCOperands()
1958 ISD::SETUNE, OutputChain, IsSignaling); in FloatExpandSetCCOperands()
1961 RHSHi, CCCode, OutputChain, IsSignaling); in FloatExpandSetCCOperands()
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| H A D | LegalizeVectorOps.cpp | 1706 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandSETCC() local
1735 EVL, NeedInvert, dl, Chain, IsSignaling); in ExpandSETCC()
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| H A D | LegalizeTypes.h | 679 SDValue &Chain, bool IsSignaling = false);
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| H A D | TargetLowering.cpp | 306 bool IsSignaling) const { in softenSetCCOperands()
10891 bool IsSignaling) const { in LegalizeSetCCCondCode()
11005 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling); in LegalizeSetCCCondCode()
11006 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2, Chain, IsSignaling); in LegalizeSetCCCondCode()
11014 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling); in LegalizeSetCCCondCode()
11015 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2, Chain, IsSignaling); in LegalizeSetCCCondCode()
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| H A D | LegalizeDAG.cpp | 4022 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandNode() local
4035 Chain, IsSignaling); in ExpandNode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Support/ |
| H A D | APFloat.cpp | 3144 bool IsSignaling = str.front() == 's' || str.front() == 'S'; in convertFromStringSpecials() local
3145 if (IsSignaling) { in convertFromStringSpecials()
3156 makeNaN(IsSignaling, IsNegative); in convertFromStringSpecials()
3182 makeNaN(IsSignaling, IsNegative, &Payload); in convertFromStringSpecials()
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| /freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 14103 bool IsSignaling) { in EmitX86BuiltinExpr() argument
14106 if (IsSignaling) in EmitX86BuiltinExpr()
16020 bool IsSignaling; in EmitX86BuiltinExpr() local
16024 case 0x00: Pred = FCmpInst::FCMP_OEQ; IsSignaling = false; break; in EmitX86BuiltinExpr()
16025 case 0x01: Pred = FCmpInst::FCMP_OLT; IsSignaling = true; break; in EmitX86BuiltinExpr()
16026 case 0x02: Pred = FCmpInst::FCMP_OLE; IsSignaling = true; break; in EmitX86BuiltinExpr()
16027 case 0x03: Pred = FCmpInst::FCMP_UNO; IsSignaling = false; break; in EmitX86BuiltinExpr()
16028 case 0x04: Pred = FCmpInst::FCMP_UNE; IsSignaling = false; break; in EmitX86BuiltinExpr()
16045 IsSignaling = !IsSignaling; in EmitX86BuiltinExpr()
16122 if (IsSignaling) in EmitX86BuiltinExpr()
[all …]
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| H A D | CGExprScalar.cpp | 862 llvm::CmpInst::Predicate FCmpOpc, bool IsSignaling);
4297 bool IsSignaling) { in EmitCompare() argument
4393 if (!IsSignaling) in EmitCompare()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1208 bool IsSignaling = false) {
1216 return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL,
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| H A D | TargetLowering.h | 3774 bool IsSignaling = false) const;
5330 SDValue &Chain, bool IsSignaling = false) const;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5799 bool IsSignaling = Node->getOpcode() == X86ISD::STRICT_FCMPS; in Select() local
5805 Opc = IsSignaling ? X86::COM_Fpr32 : X86::UCOM_Fpr32; in Select()
5808 Opc = IsSignaling ? X86::COM_Fpr64 : X86::UCOM_Fpr64; in Select()
5811 Opc = IsSignaling ? X86::COM_Fpr80 : X86::UCOM_Fpr80; in Select()
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| H A D | X86ISelLowering.cpp | 23083 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerVSETCC() local
23118 if (IsStrict && IsAlwaysSignaling && !IsSignaling) in LowerVSETCC()
23122 if (IsStrict && !IsAlwaysSignaling && IsSignaling) { in LowerVSETCC()
23182 SSECC |= (IsAlwaysSignaling ^ IsSignaling) << 4; in LowerVSETCC()
23705 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC() local
23707 DAG.getNode(IsSignaling ? X86ISD::STRICT_FCMPS : X86ISD::STRICT_FCMP, in LowerSETCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 2368 bool IsSignaling);
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3149 bool IsSignaling) { in emitStrictFPComparison() argument
3164 IsSignaling ? AArch64ISD::STRICT_FCMPE : AArch64ISD::STRICT_FCMP; in emitStrictFPComparison()
9375 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC() local
9394 IsSignaling); in LowerSETCC()
9424 Cmp = emitStrictFPComparison(LHS, RHS, dl, DAG, Chain, IsSignaling); in LowerSETCC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10503 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerFSETCC() local
10509 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS, Chain, IsSignaling); in LowerFSETCC()
10531 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, IsSignaling); in LowerFSETCC()
10535 Cmp = getVFPCmp(LHS, RHS, DAG, dl, IsSignaling); in LowerFSETCC()
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