Searched refs:IsScaled (Results 1 – 4 of 4) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 753 bool IsScaled = !TII->hasUnscaledLdStOffset(Opc); in mergeNarrowZeroStores() local 755 int OffsetStride = IsScaled ? TII->getMemScale(*I) : 1; in mergeNarrowZeroStores()
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| H A D | AArch64ISelLowering.cpp | 5557 unsigned getGatherVecOpcode(bool IsScaled, bool IsSigned, bool NeedsExtend) { in getGatherVecOpcode() argument 5576 auto Key = std::make_tuple(IsScaled, IsSigned, NeedsExtend); in getGatherVecOpcode() 5629 bool IsScaled = MGT->isIndexScaled(); in LowerMGATHER() local 5635 if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) { in LowerMGATHER() 5717 bool IsScaled = MSC->isIndexScaled(); in LowerMSCATTER() local 5723 if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) { in LowerMSCATTER()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2677 auto [ScaledInput, IsScaled] = getScaledLogInput(DAG, DL, X, Flags); in LowerFLOGCommon() 2734 if (IsScaled) { in LowerFLOGCommon() 2739 DAG.getNode(ISD::SELECT, DL, VT, IsScaled, ShiftK, Zero, Flags); in LowerFLOGCommon() 2763 auto [ScaledInput, IsScaled] = getScaledLogInput(DAG, SL, Src, Flags); in LowerFLOGUnsafe() 2771 SDValue ResultOffset = DAG.getNode(ISD::SELECT, SL, VT, IsScaled, in LowerFLOGUnsafe()
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| H A D | AMDGPULegalizerInfo.cpp | 3278 auto [ScaledInput, IsScaled] = getScaledLogInput(B, X, Flags); in legalizeFlogCommon() 3343 auto Shift = B.buildSelect(Ty, IsScaled, ShiftK, Zero, Flags); in legalizeFlogCommon() 3362 auto [ScaledInput, IsScaled] = getScaledLogInput(B, Src, Flags); in legalizeFlogUnsafe() 3370 B.buildSelect(Ty, IsScaled, ScaledResultOffset, Zero, Flags); in legalizeFlogUnsafe()
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