| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 35 bool IsRet; member
39 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet) in RISCVOutgoingValueAssigner()
41 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {} in RISCVOutgoingValueAssigner()
52 LocInfo, Flags, State, Info.IsFixed, IsRet, Info.Ty, in assignArg()
173 bool IsRet; member
177 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet) in RISCVIncomingValueAssigner()
179 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {} in RISCVIncomingValueAssigner()
193 LocInfo, Flags, State, /*IsFixed=*/true, IsRet, Info.Ty, in assignArg()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 839 bool IsFixed, bool IsRet, Type *OrigTy,
845 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
849 bool IsRet, CallLoweringInfo *CLI,
986 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
992 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
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| H A D | RISCVISelLowering.cpp | 17428 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, in CC_RISCV() argument
17445 if (!LocVT.isVector() && IsRet && ValNo > 1) in CC_RISCV()
17604 if (IsRet) in CC_RISCV()
17679 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, in analyzeInputArgs() argument
17693 if (IsRet) in analyzeInputArgs()
17700 ArgFlags, CCInfo, /*IsFixed=*/true, IsRet, ArgTy, *this, in analyzeInputArgs()
17711 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, in analyzeOutputArgs() argument
17726 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this, in analyzeOutputArgs()
17906 bool IsFixed, bool IsRet, Type *OrigTy, in CC_RISCV_FastCC() argument
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.h | 251 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
255 bool IsRet, CallLoweringInfo *CLI,
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| H A D | LoongArchISelLowering.cpp | 3537 CCState &State, bool IsFixed, bool IsRet, in CC_LoongArch() argument
3546 if (IsRet && ValNo > 1) in CC_LoongArch()
3688 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, in analyzeInputArgs() argument
3694 if (IsRet) in analyzeInputArgs()
3701 CCInfo, /*IsFixed=*/true, IsRet, ArgTy)) { in analyzeInputArgs()
3711 const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, in analyzeOutputArgs() argument
3719 CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) { in analyzeOutputArgs()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 2611 bit IsRet = isRet;
2788 let ColFields = ["IsRet"];
|