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Searched refs:IsROTL (Results 1 – 2 of 2) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2166 bool IsROTL = (Op.getOpcode() == ISD::ROTL); in SimplifyDemandedBits() local
2178 APInt Demanded0 = DemandedBits.rotr(IsROTL ? Amt : RevAmt); in SimplifyDemandedBits()
2189 DemandedBits.countr_zero() >= (IsROTL ? Amt : RevAmt)) { in SimplifyDemandedBits()
2190 Op1 = TLO.DAG.getConstant(IsROTL ? Amt : RevAmt, dl, Op1.getValueType()); in SimplifyDemandedBits()
2194 DemandedBits.countl_zero() >= (IsROTL ? RevAmt : Amt)) { in SimplifyDemandedBits()
2195 Op1 = TLO.DAG.getConstant(IsROTL ? RevAmt : Amt, dl, Op1.getValueType()); in SimplifyDemandedBits()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp29836 bool IsROTL = Opcode == ISD::ROTL; in LowerRotate() local
29870 if (!IsROTL) { in LowerRotate()
29890 assert(IsROTL && "Only ROTL expected"); in LowerRotate()
29957 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate()
29997 if (IsROTL) in LowerRotate()
30022 if (!IsROTL && !useVPTERNLOG(Subtarget, VT)) { in LowerRotate()
30024 IsROTL = true; in LowerRotate()
30027 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate()
30082 if (!IsROTL) { in LowerRotate()
30084 IsROTL = true; in LowerRotate()
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