Searched refs:IsPre (Results 1 – 8 of 8) sorted by relevance
1470 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad() local1480 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost; in tryIndexedLoad()1483 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1485 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in tryIndexedLoad()1487 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1500 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in tryIndexedLoad()1520 Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost; in tryIndexedLoad()1522 Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost; in tryIndexedLoad()1524 Opcode = IsPre ? AArch64::LDRSpre : AArch64::LDRSpost; in tryIndexedLoad()1526 Opcode = IsPre ? AArch64::LDRDpre : AArch64::LDRDpost; in tryIndexedLoad()[all …]
1267 bool IsPre, MachineRegisterInfo &MRI) const override;
24224 Register Offset, bool IsPre, in isIndexingLegal() argument
61 bool IsPre; member
768 bool IsPre = AM == ISD::PRE_INC; in tryIndexedLoad() local785 if (LoadVT == MVT::i8 && IsPre) in tryIndexedLoad()789 else if (LoadVT == MVT::i16 && IsPre) in tryIndexedLoad()793 else if (LoadVT == MVT::i32 && IsPre) in tryIndexedLoad()797 else if (LoadVT == MVT::i64 && IsPre) in tryIndexedLoad()
5621 bool IsPre = ExtLd.isPre(); in selectIndexedExtLoad() local5634 Opc = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost; in selectIndexedExtLoad()5636 Opc = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost; in selectIndexedExtLoad()5639 Opc = IsPre ? AArch64::LDRBBpre : AArch64::LDRBBpost; in selectIndexedExtLoad()5646 Opc = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost; in selectIndexedExtLoad()5648 Opc = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost; in selectIndexedExtLoad()5651 Opc = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in selectIndexedExtLoad()5657 Opc = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in selectIndexedExtLoad()5660 Opc = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in selectIndexedExtLoad()
1269 MatchInfo.IsPre = findPreIndexCandidate(LdSt, MatchInfo.Addr, MatchInfo.Base, in matchCombineIndexedLoadStore()1271 if (!MatchInfo.IsPre && in matchCombineIndexedLoadStore()1307 MIB.addImm(MatchInfo.IsPre); in applyCombineIndexedLoadStore()
3720 bool IsPre, MachineRegisterInfo &MRI) const { in isIndexingLegal() argument