Searched refs:IsAGPR (Results 1 – 7 of 7) sorted by relevance
355 IsAGPR = true; in analyzeResourceUsage()365 IsAGPR = true; in analyzeResourceUsage()375 IsAGPR = true; in analyzeResourceUsage()385 IsAGPR = true; in analyzeResourceUsage()395 IsAGPR = true; in analyzeResourceUsage()405 IsAGPR = true; in analyzeResourceUsage()415 IsAGPR = true; in analyzeResourceUsage()425 IsAGPR = true; in analyzeResourceUsage()435 IsAGPR = true; in analyzeResourceUsage()445 IsAGPR = true; in analyzeResourceUsage()[all …]
1342 const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC); in buildSpillLoadStore() local1347 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()1604 if (IsAGPR) { in buildSpillLoadStore()1642 MIB.addReg(TmpOffsetVGPR, getKillRegState(IsLastSubReg && !IsAGPR)); in buildSpillLoadStore()1670 if (!IsAGPR && NeedSuperRegDef) in buildSpillLoadStore()1673 if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) { in buildSpillLoadStore()
118 bool IsAGPR; member734 IsAGPR = LSO.TRI->hasAGPRs(LSO.getDataRegClass(*MI)); in setMI()2262 AddrList.front().IsAGPR == CI.IsAGPR && in addInstToMergeableList()2318 if (CI.InstClass == DS_WRITE && CI.IsAGPR) { in collectMergeableInsts()
310 bool IsAGPR = TRI->isAGPRClass(DstRC); in foldVGPRCopyIntoRegSequence() local325 if (IsAGPR) { in foldVGPRCopyIntoRegSequence()
5666 bool IsAGPR = RI.isAGPR(MRI, MO->getReg()); in isOperandLegal() local5667 if (IsAGPR && !ST.hasMAIInsts()) in isOperandLegal()5670 if (IsAGPR && in isOperandLegal()5680 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isOperandLegal()5684 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isOperandLegal()5690 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isOperandLegal()9806 bool IsAGPR = RI.isAGPR(MRI, DataReg); in enforceOperandRCAlignment() local9808 IsAGPR ? &AMDGPU::AGPR_32RegClass : &AMDGPU::VGPR_32RegClass); in enforceOperandRCAlignment()9811 MRI.createVirtualRegister(IsAGPR ? &AMDGPU::AReg_64_Align2RegClass in enforceOperandRCAlignment()
504 bool IsAGPR = false; in getAVOperandEncoding() local519 IsAGPR = true; in getAVOperandEncoding()521 Op = Idx | (IsVGPROrAGPR << 8) | (IsAGPR << 9); in getAVOperandEncoding()
1586 bool IsAGPR = Val & 512; in decodeSrcOp() local1590 return createRegOperand(IsAGPR ? getAgprClassId(Width) in decodeSrcOp()