| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1145 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
1183 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1530 MVT IntermediateVT; in computeRegisterProperties() local
1533 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1598 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown() argument
1613 IntermediateVT = RegisterEVT; in getVectorTypeBreakdown()
1644 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1645 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1669 IntermediateVT = NewVT; in getVectorTypeBreakdown()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 351 EVT IntermediateVT; in getCopyFromPartsVector() local
358 *DAG.getContext(), *CallConv, ValueVT, IntermediateVT, in getCopyFromPartsVector()
395 IntermediateVT.isVector() in getCopyFromPartsVector()
397 *DAG.getContext(), IntermediateVT.getScalarType(), in getCopyFromPartsVector()
398 IntermediateVT.getVectorElementCount() * NumParts) in getCopyFromPartsVector()
400 IntermediateVT.getScalarType(), in getCopyFromPartsVector()
402 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
747 EVT IntermediateVT; in getCopyToPartsVector() local
770 if (IntermediateVT.isVector()) in getCopyToPartsVector()
776 *DAG.getContext(), IntermediateVT.getScalarType(), *DestEltCnt); in getCopyToPartsVector()
[all …]
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| H A D | SelectionDAG.cpp | 2435 EVT IntermediateVT; in getReducedAlign() local
2438 TLI->getVectorTypeBreakdown(*getContext(), VT, IntermediateVT, in getReducedAlign()
2440 Ty = IntermediateVT.getTypeForEVT(*getContext()); in getReducedAlign()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 172 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
181 IntermediateVT = MVT::i1; in getVectorTypeBreakdownForCallingConv()
190 IntermediateVT = MVT::v32i1; in getVectorTypeBreakdownForCallingConv()
199 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT, in getVectorTypeBreakdownForCallingConv()
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| H A D | X86ISelLowering.h | 1531 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 303 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | MipsISelLowering.cpp | 124 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
127 IntermediateVT = getRegisterTypeForCallingConv(Context, CC, VT); in getVectorTypeBreakdownForCallingConv()
128 RegisterVT = IntermediateVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
132 IntermediateVT = VT.getVectorElementType(); in getVectorTypeBreakdownForCallingConv()
134 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
135 return NumIntermediates * getNumRegisters(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.h | 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | SIISelLowering.cpp | 1044 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
1056 IntermediateVT = MVT::v2bf16; in getVectorTypeBreakdownForCallingConv()
1059 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1067 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1075 IntermediateVT = ScalarVT; in getVectorTypeBreakdownForCallingConv()
1083 IntermediateVT = ScalarVT; in getVectorTypeBreakdownForCallingConv()
1090 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1097 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 497 EVT &IntermediateVT,
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| H A D | RISCVISelLowering.cpp | 2202 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
2205 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
2207 if (RV64LegalI32 && Subtarget.is64Bit() && IntermediateVT == MVT::i32) in getVectorTypeBreakdownForCallingConv()
2208 IntermediateVT = MVT::i64; in getVectorTypeBreakdownForCallingConv()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1126 EVT &IntermediateVT,
1134 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
1136 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates, in getVectorTypeBreakdownForCallingConv()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 992 EVT &IntermediateVT,
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| H A D | AArch64ISelLowering.cpp | 27081 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
27087 assert(IntermediateVT == RegisterVT && "Unexpected VT mismatch!"); in getVectorTypeBreakdownForCallingConv()
27098 IntermediateVT = NewVT; in getVectorTypeBreakdownForCallingConv()
27115 IntermediateVT = RegisterVT = MVT::v16i8; in getVectorTypeBreakdownForCallingConv()
27118 IntermediateVT = RegisterVT = MVT::v8i16; in getVectorTypeBreakdownForCallingConv()
27121 IntermediateVT = RegisterVT = MVT::v4i32; in getVectorTypeBreakdownForCallingConv()
27124 IntermediateVT = RegisterVT = MVT::v2i64; in getVectorTypeBreakdownForCallingConv()
27127 IntermediateVT = RegisterVT = MVT::v8f16; in getVectorTypeBreakdownForCallingConv()
27130 IntermediateVT = RegisterVT = MVT::v4f32; in getVectorTypeBreakdownForCallingConv()
27133 IntermediateVT = RegisterVT = MVT::v2f64; in getVectorTypeBreakdownForCallingConv()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8605 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; in LowerINT_TO_FPVector() local
8626 Arrange = DAG.getBitcast(IntermediateVT, Arrange); in LowerINT_TO_FPVector()
8630 IntermediateVT.getVectorNumElements()); in LowerINT_TO_FPVector()
8632 Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange, in LowerINT_TO_FPVector()
8635 Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange); in LowerINT_TO_FPVector()
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