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Searched refs:IntID (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMapAsm2IntrinV62.gen.td9 multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
32 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
39 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
47 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
70 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
85 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2),
92 def: Pat<(IntID IntRegs:$src1),
99 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
[all …]
H A DHexagonIntrinsicsV60.td84 multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
91 def: Pat<(IntID HvxVR:$src1),
99 def: Pat<(IntID HvxWR:$src1),
107 def: Pat<(IntID HvxQR:$src1),
115 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
123 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
139 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
147 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
155 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
[all …]
H A DHexagonIntrinsics.td11 class T_R_pat <InstHexagon MI, Intrinsic IntID>
12 : Pat <(IntID I32:$Rs),
15 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
16 : Pat <(IntID I32:$Rs, I32:$Rt),
19 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
20 : Pat <(IntID I32:$Rs, I64:$Rt),
187 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
372 def: Pat<(!cast<Intrinsic>(IntID#"_128B")
380 def: Pat<(!cast<Intrinsic>(IntID#"_128B")
398 def: Pat<(!cast<Intrinsic>(IntID#"_128B")
[all …]
H A DHexagonOptimizeSZextends.cpp47 bool intrinsicAlreadySextended(Intrinsic::ID IntID);
56 bool HexagonOptimizeSZextends::intrinsicAlreadySextended(Intrinsic::ID IntID) { in intrinsicAlreadySextended() argument
57 switch(IntID) { in intrinsicAlreadySextended()
H A DHexagonISelLowering.cpp3845 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked in emitLoadLinked() local
3847 Function *Fn = Intrinsic::getDeclaration(M, IntID); in emitLoadLinked()
3866 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked in emitStoreConditional() local
3868 Function *Fn = Intrinsic::getDeclaration(M, IntID); in emitStoreConditional()
H A DHexagonVectorCombine.cpp143 Value *createHvxIntrinsic(IRBuilderBase &Builder, Intrinsic::ID IntID,
2569 Intrinsic::ID IntID, Type *RetTy, in createHvxIntrinsic() argument
2597 Function *IntrFn = Intrinsic::getDeclaration(F.getParent(), IntID, ArgTys); in createHvxIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/ObjCARC/
H A DARCRuntimeEntryPoints.h138 Function *getIntrinsicEntryPoint(Function *&Decl, Intrinsic::ID IntID) { in getIntrinsicEntryPoint() argument
142 return Decl = Intrinsic::getDeclaration(TheModule, IntID); in getIntrinsicEntryPoint()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td268 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
271 [(set Ty:$RT, (IntID Ty:$RA, Ty:$RB, Ty:$RC))]>;
288 (IntID In1Ty:$RA, In1Ty:$RB, In2Ty:$RC))]>;
294 [(set Ty:$VD, (IntID Ty:$VA, Ty:$VB))]>;
302 [(set OutTy:$VD, (IntID InTy:$VA, InTy:$VB))]>;
310 [(set OutTy:$VD, (IntID In1Ty:$VA, In2Ty:$VB))]>;
313 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
316 [(set v4f32:$VD, (IntID v4f32:$VB))]>;
324 [(set OutTy:$VD, (IntID InTy:$VB))]>;
329 [(set Ty:$VD, (IntID Ty:$VA))]>;
[all …]
H A DPPCISelDAGToDAG.cpp5347 auto IntID = N->getConstantOperandVal(0); in Select() local
5348 if (IntID == Intrinsic::ppc_fsels) { in Select()
5354 if (IntID == Intrinsic::ppc_bcdadd_p || IntID == Intrinsic::ppc_bcdsub_p) { in Select()
5357 IntID == Intrinsic::ppc_bcdadd_p ? PPC::BCDADD_rec : PPC::BCDSUB_rec; in Select()
5434 switch (IntID) { in Select()
/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/
H A DCGObjC.cpp2157 static llvm::Function *getARCIntrinsic(llvm::Intrinsic::ID IntID, in getARCIntrinsic() argument
2159 llvm::Function *fn = CGM.getIntrinsic(IntID); in getARCIntrinsic()
2169 llvm::Function *&fn, llvm::Intrinsic::ID IntID, in emitARCValueOperation() argument
2175 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCValueOperation()
2193 llvm::Intrinsic::ID IntID) { in emitARCLoadOperation() argument
2195 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCLoadOperation()
2205 llvm::Intrinsic::ID IntID, in emitARCStoreOperation() argument
2210 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCStoreOperation()
2229 llvm::Intrinsic::ID IntID) { in emitARCCopyOperation() argument
2233 fn = getARCIntrinsic(IntID, CGF.CGM); in emitARCCopyOperation()
H A DCodeGenFunction.h4338 unsigned IntID);
4341 unsigned IntID);
4353 unsigned IntID);
4356 unsigned IntID);
4359 unsigned IntID);
4370 unsigned IntID);
4373 unsigned IntID);
4376 unsigned IntID);
4379 unsigned IntID);
H A DCGBuiltin.cpp8154 TblF = CGF.CGM.getIntrinsic(IntID, ResTy); in packTBLDVectorList()
9552 unsigned IntID; in EmitSVEPredicateCast() local
9594 F = CGM.getIntrinsic(IntID, OverloadedTy); in EmitSVEGatherLoad()
9652 F = CGM.getIntrinsic(IntID, OverloadedTy); in EmitSVEScatterStore()
9726 switch (IntID) { in EmitSVEStructLoad()
9756 Function *F = CGM.getIntrinsic(IntID, {VTy}); in EmitSVEStructLoad()
9774 switch (IntID) { in EmitSVEStructStore()
9983 Function *F = CGM.getIntrinsic(IntID); in EmitSMELd1St1()
9991 Function *F = CGM.getIntrinsic(IntID, VecTy); in EmitSMEReadWrite()
10005 Function *F = CGM.getIntrinsic(IntID, {}); in EmitSMEZero()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/IR/
H A DFunction.cpp446 if (IntID) in Function()
447 setAttributes(Intrinsic::getAttributes(getContext(), IntID)); in Function()
871 return isTargetIntrinsic(IntID); in isTargetIntrinsic()
920 IntID = Intrinsic::not_intrinsic; in updateAfterNameChange()
924 IntID = lookupIntrinsicID(Name); in updateAfterNameChange()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DGlobalValue.h173 Intrinsic::ID IntID = (Intrinsic::ID)0U;
H A DFunction.h230 Intrinsic::ID getIntrinsicID() const LLVM_READONLY { return IntID; } in getIntrinsicID()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4796 SDValue IntID = in lowerVECTOR_SHUFFLE() local
4799 IntID, in lowerVECTOR_SHUFFLE()
8924 SDValue IntID = DAG.getTargetConstant( in LowerINTRINSIC_VOID() local
10022 SDValue IntID = DAG.getTargetConstant( in lowerFixedLengthVectorLoadToRVV() local
10080 SDValue IntID = DAG.getTargetConstant( in lowerFixedLengthVectorStoreToRVV() local
10127 unsigned IntID = in lowerMaskedLoad() local
10193 unsigned IntID = in lowerMaskedStore() local
11142 unsigned IntID = in lowerMaskedGather() local
11241 unsigned IntID = in lowerMaskedScatter() local
14913 SDValue IntID = in performCONCAT_VECTORSCombine() local
[all …]
H A DRISCVISelDAGToDAG.cpp109 SDValue IntID = in PreprocessISelDAG() local
112 IntID, in PreprocessISelDAG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2196 Intrinsic::ID IntID = in computeKnownBitsForTargetNode() local
2198 switch (IntID) { in computeKnownBitsForTargetNode()
24903 Intrinsic::ID IntID = in ReplaceNodeResults() local
24905 switch (IntID) { in ReplaceNodeResults()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp20089 Intrinsic::ID IntID = in computeKnownBitsForTargetNode() local
20091 switch (IntID) { in computeKnownBitsForTargetNode()