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Searched refs:InstrStage (Results 1 – 25 of 38) sorted by relevance

12

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedule440.td149 InstrStage<1, [P440_IWB]>],
157 InstrStage<1, [P440_IWB]>],
165 InstrStage<1, [P440_IWB]>],
172 InstrStage<1, [P440_IWB]>],
236 InstrStage<1, [P440_CRD]>,
243 InstrStage<1, [P440_CRD]>,
250 InstrStage<1, [P440_CRD]>,
257 InstrStage<1, [P440_CRD]>,
264 InstrStage<1, [P440_CRD]>,
271 InstrStage<1, [P440_CRD]>,
[all …]
H A DPPCScheduleE5500.td72 InstrStage<1, [E5500_CFX_0], 0>,
84 InstrStage<1, [E5500_FPU_0]>],
88 InstrStage<7, [E5500_FPU_0]>],
93 InstrStage<2, [E5500_CFX_1]>],
99 InstrStage<1, [E5500_CFX_1]>],
105 InstrStage<1, [E5500_CFX_1]>],
111 InstrStage<2, [E5500_CFX_1]>],
136 InstrStage<2, [E5500_SFX0]>],
140 InstrStage<1, [E5500_BU]>],
144 InstrStage<1, [E5500_BU]>],
[all …]
H A DPPCScheduleG4.td30 InstrItinData<IIC_IntDivW , [InstrStage<19, [G4_IU1]>]>,
31 InstrItinData<IIC_IntMFFS , [InstrStage<3, [G4_FPU1]>]>,
32 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G4_VIU1]>]>,
33 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G4_FPU1]>]>,
34 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G4_IU1]>]>,
35 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G4_IU1]>]>,
36 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4_IU1]>]>,
40 InstrItinData<IIC_BrB , [InstrStage<1, [G4_BPU]>]>,
41 InstrItinData<IIC_BrCR , [InstrStage<1, [G4_SRU]>]>,
42 InstrItinData<IIC_BrMCR , [InstrStage<1, [G4_SRU]>]>,
[all …]
H A DPPCScheduleE500mc.td74 InstrStage<8, [E500mc_FPU_0]>],
78 InstrStage<8, [E500mc_FPU_0]>],
82 InstrStage<1, [E500mc_CFX_0]>],
87 InstrStage<1, [E500mc_CFX_0]>],
92 InstrStage<1, [E500mc_CFX_0]>],
107 InstrStage<2, [E500mc_SFX0]>],
111 InstrStage<1, [E500mc_BU]>],
115 InstrStage<1, [E500mc_BU]>],
120 InstrStage<1, [E500mc_BU]>],
128 InstrStage<1, [E500mc_LSU_0]>],
[all …]
H A DPPCScheduleG5.td31 InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>,
32 InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>,
33 InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>,
34 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>,
40 InstrItinData<IIC_IntRFID , [InstrStage<1, [G5_IU2]>]>,
47 InstrItinData<IIC_BrB , [InstrStage<1, [G5_BPU]>]>,
48 InstrItinData<IIC_BrCR , [InstrStage<4, [G5_BPU]>]>,
49 InstrItinData<IIC_BrMCR , [InstrStage<2, [G5_BPU]>]>,
50 InstrItinData<IIC_BrMCRX , [InstrStage<3, [G5_BPU]>]>,
51 InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>,
[all …]
H A DPPCScheduleG4Plus.td35 InstrItinData<IIC_IntDivW , [InstrStage<23, [G4P_IU2]>]>,
36 InstrItinData<IIC_IntMFFS , [InstrStage<5, [G4P_FPU1]>]>,
37 InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [G4P_VFPU]>]>,
38 InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [G4P_FPU1]>]>,
39 InstrItinData<IIC_IntMulHW , [InstrStage<4, [G4P_IU2]>]>,
40 InstrItinData<IIC_IntMulHWU , [InstrStage<4, [G4P_IU2]>]>,
41 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4P_IU2]>]>,
48 InstrItinData<IIC_BrB , [InstrStage<1, [G4P_BPU]>]>,
49 InstrItinData<IIC_BrCR , [InstrStage<2, [G4P_IU2]>]>,
50 InstrItinData<IIC_BrMCR , [InstrStage<2, [G4P_IU2]>]>,
[all …]
H A DPPCScheduleE500.td63 InstrStage<1, [E500_MU], 0>,
64 InstrStage<14, [E500_MU]>],
69 InstrStage<4, [E500_MU]>],
74 InstrStage<4, [E500_MU]>],
79 InstrStage<4, [E500_MU]>],
94 InstrStage<2, [E500_SU0]>],
98 InstrStage<1, [E500_BU]>],
102 InstrStage<1, [E500_BU]>],
107 InstrStage<1, [E500_BU]>],
242 InstrStage<6, [E500_MU]>],
[all …]
H A DPPCScheduleG3.td25 InstrItinData<IIC_IntDivW , [InstrStage<19, [G3_IU1]>]>,
26 InstrItinData<IIC_IntMFFS , [InstrStage<1, [G3_FPU1]>]>,
27 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G3_FPU1]>]>,
28 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G3_IU1]>]>,
29 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G3_IU1]>]>,
30 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G3_IU1]>]>,
34 InstrItinData<IIC_BrB , [InstrStage<1, [G3_BPU]>]>,
35 InstrItinData<IIC_BrCR , [InstrStage<1, [G3_SRU]>]>,
36 InstrItinData<IIC_BrMCR , [InstrStage<1, [G3_SRU]>]>,
37 InstrItinData<IIC_BrMCRX , [InstrStage<1, [G3_SRU]>]>,
[all …]
H A DPPCScheduleA2.td27 InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>],
29 InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>],
31 InstrItinData<IIC_IntISEL, [InstrStage<1, [A2_XU]>],
33 InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>],
35 InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>],
37 InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>],
39 InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>],
41 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>],
43 InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>],
45 InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>],
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA8.td153 InstrStage<2, [A8_LSPipe]>],
163 InstrStage<3, [A8_LSPipe]>,
174 InstrStage<3, [A8_LSPipe]>,
180 InstrStage<1, [A8_LSPipe]>,
361 InstrStage<1, [A8_NPipe]>],
366 InstrStage<1, [A8_NPipe]>],
371 InstrStage<1, [A8_NPipe]>],
376 InstrStage<1, [A8_NPipe]>],
396 InstrStage<1, [A8_LSPipe]>,
404 InstrStage<1, [A8_LSPipe]>,
[all …]
H A DARMScheduleA9.td63 InstrStage<1, [A9_MUX0], 0>,
64 InstrStage<1, [A9_AGU], 0>,
176 InstrStage<2, [A9_ALU0]>],
181 InstrStage<2, [A9_ALU0]>],
186 InstrStage<3, [A9_ALU0]>],
458 InstrStage<1, [A9_MUX0], 0>,
461 InstrStage<1, [A9_NPipe]>],
470 InstrStage<1, [A9_NPipe]>],
479 InstrStage<1, [A9_NPipe]>],
489 InstrStage<1, [A9_NPipe]>],
[all …]
H A DARMScheduleV6.td24 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,
64 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [V6_Pipe]>,
66 InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [V6_Pipe]>,
67 InstrStage<1, [V6_Pipe]>,
69 InstrItinData<IIC_iMOVix2ld , [InstrStage<1, [V6_Pipe]>,
70 InstrStage<1, [V6_Pipe]>,
78 InstrItinData<IIC_iCMOVix2 , [InstrStage<1, [V6_Pipe]>,
133 InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [V6_Pipe]>,
138 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>,
146 InstrItinData<IIC_iPop_Br, [InstrStage<3, [V6_Pipe]>,
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepIICHVX.td126 InstrStage<1, [CVI_LD], 0>,
162 [InstrStage<1, [SLOT0], 0>,
163 InstrStage<1, [SLOT1], 0>,
164 InstrStage<1, [CVI_ST], 0>,
185 [InstrStage<1, [SLOT0], 0>,
202 [InstrStage<1, [SLOT0], 0>,
207 [InstrStage<1, [SLOT0], 0>,
269 [InstrStage<1, [SLOT0], 0>,
270 InstrStage<1, [SLOT1], 0>,
281 [InstrStage<1, [SLOT0], 0>,
[all …]
H A DHexagonDepIICScalar.td2247 [InstrStage<1, [SLOT0], 0>,
2264 [InstrStage<1, [SLOT0], 0>,
2306 [InstrStage<1, [SLOT0], 0>,
2336 [InstrStage<1, [SLOT2], 0>,
2341 [InstrStage<1, [SLOT2], 0>,
2346 [InstrStage<1, [SLOT2], 0>,
2379 [InstrStage<1, [SLOT0], 0>,
2388 [InstrStage<1, [SLOT2], 0>,
2414 [InstrStage<1, [SLOT2], 0>,
2451 [InstrStage<1, [SLOT2], 0>,
[all …]
H A DHexagonIICScalar.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
17 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
18 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
19 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
20 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
26 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
28 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
H A DHexagonScheduleV5.td14 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
15 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
16 InstrStage<1, [SLOT2, SLOT3]>]>,
17 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>]>,
18 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>
24 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
25 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>
H A DHexagonScheduleV55.td12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
14 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
15 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
16 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
17 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
24 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>,
25 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
H A DHexagonScheduleV67T.td11 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
13 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
14 InstrStage<1, [SLOT2, SLOT3]>],
17 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>],
19 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
29 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>],
32 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>],
H A DHexagonScheduleV71T.td12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
14 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
15 InstrStage<1, [SLOT2, SLOT3]>],
18 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>],
20 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
30 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>],
33 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>],
H A DHexagonIICHVX.td15 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
16 InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>],
25 [InstrStage<1, [SLOT0], 0>,
26 InstrStage<1, [SLOT1], 0>,
27 InstrStage<1, [CVI_ST], 0>,
28 InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>];
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSchedule.td389 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
390 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
391 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
392 InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
393 InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
394 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
395 InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
396 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
397 InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>,
398 InstrItinData<II_AUIPC , [InstrStage<1, [ALU]>]>,
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcSchedule.td45 InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
52 InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [5, 1]>,
53 InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [5, 1]>,
54 InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
63 InstrItinData<IIC_fpu_abs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
66 InstrItinData<IIC_fpu_stod, [InstrStage<1, [LEONFPU]>], [2, 1]>
72 InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
79 InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [1, 1]>,
80 InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [4, 1]>,
81 InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp44 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
45 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
94 InstrStage::FuncUnits FUs = (*this)[i]; in dump()
128 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
145 InstrStage::FuncUnits freeUnits = IS->getUnits(); in getHazardType()
147 case InstrStage::Required: in getHazardType()
151 case InstrStage::Reserved: in getHazardType()
196 InstrStage::FuncUnits freeUnits = IS->getUnits(); in EmitInstruction()
198 case InstrStage::Required: in EmitInstruction()
202 case InstrStage::Reserved: in EmitInstruction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600Schedule.td31 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
32 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
33 InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
34 InstrItinData<XALU, [InstrStage<1, [ALU_X]>]>,
35 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
43 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
44 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
45 InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>,
46 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h59 struct InstrStage { struct
114 const InstrStage *Stages = nullptr; ///< Array of stages selected
121 InstrItineraryData(const MCSchedModel &SM, const InstrStage *S, in InstrItineraryData()
136 const InstrStage *beginStage(unsigned ItinClassIndx) const { in beginStage()
142 const InstrStage *endStage(unsigned ItinClassIndx) const { in endStage()
158 for (const InstrStage *IS = beginStage(ItinClassIndx), in getStageLatency()

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