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Searched refs:Instr (Results 1 – 25 of 141) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp711 IRBuilder<> B{Instr}; in narrowSDivOrSRem()
717 auto *BO = B.CreateBinOp(Instr->getOpcode(), LHS, RHS, Instr->getName()); in narrowSDivOrSRem()
718 auto *Sext = B.CreateSExt(BO, Instr->getType(), Instr->getName() + ".sext"); in narrowSDivOrSRem()
724 Instr->eraseFromParent(); in narrowSDivOrSRem()
743 Instr->eraseFromParent(); in expandUDivOrURem()
777 IRBuilder<> B(Instr); in expandUDivOrURem()
802 Instr->eraseFromParent(); in expandUDivOrURem()
830 IRBuilder<> B{Instr}; in narrowUDivOrURem()
836 auto *BO = B.CreateBinOp(Instr->getOpcode(), LHS, RHS, Instr->getName()); in narrowUDivOrURem()
837 auto *Zext = B.CreateZExt(BO, Instr->getType(), Instr->getName() + ".zext"); in narrowUDivOrURem()
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H A DGuardWidening.cpp157 Instruction *Instr, const df_iterator<DomTreeNode *> &DFSI,
375 Instruction *Instr, const df_iterator<DomTreeNode *> &DFSI, in eliminateInstrViaWidening() argument
379 parseWidenableGuard(Instr, ChecksToHoist); in eliminateInstrViaWidening()
400 auto E = Instr->getParent() == CurBB ? find(GuardsInCurBB, Instr) in eliminateInstrViaWidening()
425 auto Score = computeWideningScore(Instr, Candidate, WideningPoint, in eliminateInstrViaWidening()
437 LLVM_DEBUG(dbgs() << "Did not eliminate guard " << *Instr << "\n"); in eliminateInstrViaWidening()
442 assert(DT.dominates(BestSoFar, Instr) && "Should be!"); in eliminateInstrViaWidening()
444 LLVM_DEBUG(dbgs() << "Widening " << *Instr << " into " << *BestSoFar in eliminateInstrViaWidening()
450 auto NewGuardCondition = ConstantInt::getTrue(Instr->getContext()); in eliminateInstrViaWidening()
451 setCondition(Instr, NewGuardCondition); in eliminateInstrViaWidening()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A DELF_aarch64.cpp194 if (!aarch64::isADR(Instr)) in addSingleRelocation()
211 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
222 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
233 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
244 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
255 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
266 if (!aarch64::isMoveWideImm16(Instr) || in addSingleRelocation()
277 if (!aarch64::isMoveWideImm16(Instr) || in addSingleRelocation()
288 if (!aarch64::isMoveWideImm16(Instr) || in addSingleRelocation()
299 if (!aarch64::isMoveWideImm16(Instr) || in addSingleRelocation()
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H A DMachO_arm64.cpp352 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
353 if ((Instr & 0x7fffffff) != 0x14000000) in addRelocations()
396 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
397 if ((Instr & 0xffffffe0) != 0x90000000) in addRelocations()
416 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
417 uint32_t EncodedAddend = (Instr & 0x003FFC00) >> 10; in addRelocations()
430 uint32_t Instr = *(const ulittle32_t *)FixupContent; in addRelocations() local
431 if ((Instr & 0xfffffc00) != 0xf9400000) in addRelocations()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.h21 bool IsCPSRDead(const InstrType *Instr);
24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument
25 switch (Instr->getOpcode()) { in isV8EligibleForIT()
52 return IsCPSRDead(Instr); in isV8EligibleForIT()
79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
H A DMVETPAndVPTOptimisationsPass.cpp608 if (Instr.getNumOperands() == 0) in IsWritingToVCCR()
635 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT)) in ReplaceRegisterUseWithVPNOT()
871 if (!IsVCMP(Instr.getOpcode())) { in ReplaceVCMPsByVPNOTs()
873 if (IsWritingToVCCR(Instr)) in ReplaceVCMPsByVPNOTs()
879 PrevVCMP = &Instr; in ReplaceVCMPsByVPNOTs()
889 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT)) in ReplaceVCMPsByVPNOTs()
890 .add(Instr.getOperand(0)) in ReplaceVCMPsByVPNOTs()
895 Instr.dump()); in ReplaceVCMPsByVPNOTs()
904 DeadInstructions.push_back(&Instr); in ReplaceVCMPsByVPNOTs()
973 auto VPNot = BuildMI(MBB, &Instr, Instr.getDebugLoc(), in ReplaceConstByVPNOTs()
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H A DThumb1InstrInfo.cpp144 unsigned Instr; in expandLoadStackGuard() local
146 Instr = ARM::tLDRLIT_ga_pcrel; in expandLoadStackGuard()
148 Instr = ARM::t2MOVi32imm; in expandLoadStackGuard()
150 Instr = ARM::tMOVi32imm; in expandLoadStackGuard()
152 Instr = ARM::tLDRLIT_ga_abs; in expandLoadStackGuard()
153 expandLoadStackGuardBase(MI, Instr, ARM::tLDRi); in expandLoadStackGuard()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp51 MachineInstr *Instr; member in __anon6eb6162d0111::RegSeqInfo
58 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo()
59 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo()
70 return RSI.Instr == Instr; in operator ==()
184 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
185 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
224 RSI->Instr->eraseFromParent(); in RebuildVector()
227 RSI->Instr = NewMI; in RebuildVector()
311 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
359 RemoveMI(CandidateRSI.Instr); in runOnMachineFunction()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch64.h355 inline bool isLoadStoreImm12(uint32_t Instr) { in isLoadStoreImm12() argument
360 inline bool isTestAndBranchImm14(uint32_t Instr) { in isTestAndBranchImm14() argument
365 inline bool isCondBranchImm19(uint32_t Instr) { in isCondBranchImm19() argument
370 inline bool isCompAndBranchImm19(uint32_t Instr) { in isCompAndBranchImm19() argument
375 inline bool isADR(uint32_t Instr) { in isADR() argument
377 return (Instr & ADRMask) == 0x10000000; in isADR()
389 if (isLoadStoreImm12(Instr)) { in getPageOffset12Shift()
390 uint32_t ImplicitShift = Instr >> 30; in getPageOffset12Shift()
392 if ((Instr & Vec128Mask) == Vec128Mask) in getPageOffset12Shift()
402 inline bool isMoveWideImm16(uint32_t Instr) { in isMoveWideImm16() argument
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
94 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
96 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
98 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
112 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
113 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
115 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
116 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h451 : Alignment(Alignment), InsertPos(Instr) { in InterleaveGroup()
456 Members[0] = Instr; in InterleaveGroup()
507 Members[Key] = Instr; in insertMember()
521 uint32_t getIndex(const InstTy *Instr) const { in getIndex() argument
523 if (I.second == Instr) in getIndex()
623 bool isInterleaved(Instruction *Instr) const { in isInterleaved() argument
624 return InterleaveGroupMap.contains(Instr); in isInterleaved()
632 return InterleaveGroupMap.lookup(Instr); in getInterleaveGroup()
707 assert(!InterleaveGroupMap.count(Instr) && in createInterleaveGroup()
709 InterleaveGroupMap[Instr] = in createInterleaveGroup()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp68 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
165 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
182 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, in getInstruction()
185 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this, in getInstruction()
190 switch (Instr.getOpcode()) { in getInstruction()
202 auto& Op = Instr.getOperand(1); in getInstruction()
212 auto Op = Instr.getOperand(0); in getInstruction()
213 Instr.clear(); in getInstruction()
214 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
215 Instr.addOperand(Op); in getInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDbgEntityHistoryCalculator.h78 Entry(const MachineInstr *Instr, EntryKind Kind) in Entry() argument
79 : Instr(Instr, Kind), EndIndex(NoEntry) {} in Entry()
81 const MachineInstr *getInstr() const { return Instr.getPointer(); } in getInstr()
83 EntryKind getEntryKind() const { return Instr.getInt(); } in getEntryKind()
92 PointerIntPair<const MachineInstr *, 1, EntryKind> Instr;
H A DRDFGraph.h389 using Instr = NodeAddr<InstrNode *>; variable
777 void pushAllDefs(Instr IA, DefStackMap &DM);
794 Ref getNextRelated(Instr IA, Ref RA) const;
795 Ref getNextShadow(Instr IA, Ref RA, bool Create);
797 NodeList getRelatedRefs(Instr IA, Ref RA) const;
856 Def newDef(Instr Owner, RegisterRef RR, uint16_t Flags = NodeAttrs::PhiRef);
863 std::pair<Ref, Ref> locateNextRef(Instr IA, Ref RA, Predicate P) const;
872 void pushClobbers(Instr IA, DefStackMap &DM);
873 void pushDefs(Instr IA, DefStackMap &DM);
883 Instr IA = RA.Addr->getOwner(*this); in removeFromOwner()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PromoteConstant.cpp280 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
284 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
287 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
291 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
295 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
299 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
304 if (isa<const LandingPadInst>(Instr)) in shouldConvertUse()
308 if (isa<const SwitchInst>(Instr)) in shouldConvertUse()
312 if (isa<const IndirectBrInst>(Instr)) in shouldConvertUse()
316 if (isa<const IntrinsicInst>(Instr)) in shouldConvertUse()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRemoveRedundantDebugValues.cpp138 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsForwardScan() local
139 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); in reduceDbgValsForwardScan()
140 Instr->eraseFromParent(); in reduceDbgValsForwardScan()
193 for (auto &Instr : DbgValsToBeRemoved) { in reduceDbgValsBackwardScan() local
194 LLVM_DEBUG(dbgs() << "removing "; Instr->dump()); in reduceDbgValsBackwardScan()
195 Instr->eraseFromParent(); in reduceDbgValsBackwardScan()
H A DMachineUniformityAnalysis.cpp32 const MachineInstr &Instr) { in markDefsDivergent() argument
37 for (auto &op : Instr.all_defs()) { in markDefsDivergent()
79 const MachineInstr &Instr) { in pushUsers() argument
80 assert(!isAlwaysUniform(Instr)); in pushUsers()
81 if (Instr.isTerminator()) in pushUsers()
83 for (const MachineOperand &op : Instr.all_defs()) { in pushUsers()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/
H A DUniformityAnalysis.cpp29 const Instruction &Instr) { in markDefsDivergent() argument
30 return markDivergent(cast<Value>(&Instr)); in markDefsDivergent()
59 const Instruction &Instr) { in pushUsers() argument
60 assert(!isAlwaysUniform(Instr)); in pushUsers()
61 if (Instr.isTerminator()) in pushUsers()
63 pushUsers(cast<Value>(&Instr)); in pushUsers()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXImageOptimizer.cpp63 for (Instruction &Instr : BB) { in runOnFunction()
64 if (CallInst *CI = dyn_cast<CallInst>(&Instr)) { in runOnFunction()
71 Changed |= replaceIsTypePSampler(Instr); in runOnFunction()
74 Changed |= replaceIsTypePSurface(Instr); in runOnFunction()
77 Changed |= replaceIsTypePTexture(Instr); in runOnFunction()
H A DNVPTXProxyRegErasure.cpp56 void replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From,
107 void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr, in replaceRegisterUsage() argument
110 for (auto &Op : Instr.uses()) { in replaceRegisterUsage()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegBankSelect.h207 MachineInstr &Instr;
216 return Instr; in getPointImpl()
217 return Instr.getNextNode() ? *Instr.getNextNode() in getPointImpl()
218 : Instr.getParent()->end(); in getPointImpl()
222 return *Instr.getParent(); in getInsertMBBImpl()
227 InstrInsertPoint(MachineInstr &Instr, bool Before = true);
/freebsd-14.2/contrib/llvm-project/llvm/lib/IR/
H A DFPEnv.cpp90 Intrinsic::ID getConstrainedIntrinsicID(const Instruction &Instr) { in getConstrainedIntrinsicID() argument
92 switch (Instr.getOpcode()) { in getConstrainedIntrinsicID()
110 if (auto *IntrinCall = dyn_cast<IntrinsicInst>(&Instr)) { in getConstrainedIntrinsicID()
/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/
H A DMCDwarf.cpp1326 switch (Instr.getOperation()) { in emitCFIInstruction()
1348 unsigned Reg = Instr.getRegister(); in emitCFIInstruction()
1361 CFAOffset += Instr.getOffset(); in emitCFIInstruction()
1363 CFAOffset = Instr.getOffset(); in emitCFIInstruction()
1370 unsigned Reg = Instr.getRegister(); in emitCFIInstruction()
1375 CFAOffset = Instr.getOffset(); in emitCFIInstruction()
1381 unsigned Reg = Instr.getRegister(); in emitCFIInstruction()
1391 unsigned Reg = Instr.getRegister(); in emitCFIInstruction()
1396 CFAOffset = Instr.getOffset(); in emitCFIInstruction()
1411 int Offset = Instr.getOffset(); in emitCFIInstruction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td300 (Br0 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
303 (Br1 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
306 (Br0 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
309 (Br1 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
313 (MV (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2))>;
316 (MV (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2))>;
339 (Br0 (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), bb:$imm16)>;
342 (Br1 (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), bb:$imm16)>;
345 (Br0 (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), bb:$imm16)>;
352 (MV (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1))>;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/Disassembler/
H A DM68kDisassembler.cpp133 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
138 DecodeStatus M68kDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
158 Result = decodeInstruction(DecoderTable80, Instr, Insn, Address, this, STI, in getInstruction()
161 Size = InstrLenTable[Instr.getOpcode()] >> 3; in getInstruction()

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