| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1575 if (!BT.has(Inp.Reg)) in findMatch()
1578 auto *FRC = HBS::getFinalVRegClass(Inp, MRI); in findMatch()
1580 if (!HBS::getSubregMask(Inp, B, W, MRI)) in findMatch()
1591 if (!HBS::isTransparentCopy(R, Inp, MRI)) in findMatch()
1614 if (HBS::isTransparentCopy(Out, Inp, MRI)) in findMatch()
2948 BitTracker::RegisterRef Inp, Out; member
3111 .addReg(G.Inp.Reg) in moveGroup()
3113 RegMap.insert(std::make_pair(G.Inp.Reg, PhiR)); in moveGroup()
3280 G.Inp.Reg = Inputs.find_first(); in processLoop()
3288 << printReg(G.Inp.Reg, HRI, G.Inp.Sub) in processLoop()
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| H A D | HexagonISelDAGToDAGHVX.cpp | 677 ResultStack(SDNode *Inp) in ResultStack()
678 : InpNode(Inp), InpTy(Inp->getValueType(0).getSimpleVT()) {} in ResultStack()
1289 OpRef Inp[2] = {Va, Vb}; in packs() local
1361 return Inp[SrcOp]; in packs()
1393 Va = Inp[Seg0 / 2]; in packs()
1396 Results.push(Hexagon::V6_vror, Ty, {Inp[Seg0 / 2], HL}); in packs()
1518 OpRef Inp[2] = { Va, Vb }; in packp() local
1526 OpRef Op = Inp[S / 2]; in packp()
2574 SDValue Inp = N->getOperand(0); in selectExtractSubvector() local
2578 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); in selectExtractSubvector()
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| H A D | HexagonISelLoweringHVX.cpp | 2453 SDValue Inp = DAG.getBitcast(IntTy, Val); in emitHvxShiftRightRnd() local
2457 SDValue And = DAG.getNode(ISD::AND, dl, IntTy, {Inp, AmtP1}); in emitHvxShiftRightRnd()
2464 SDValue Tmp1 = DAG.getNode(ShRight, dl, IntTy, Inp, AmtM1); in emitHvxShiftRightRnd()
2679 SDValue Inp = Op.getOperand(0); in EqualizeFpIntConversion() local
2680 MVT InpTy = ty(Inp); in EqualizeFpIntConversion()
2690 SDValue WInp = resizeToWidth(Inp, WInpTy, Signed, dl, DAG); in EqualizeFpIntConversion()
2786 SDValue Inp = DAG.getBitcast(ResTy, Op0); in ExpandHvxFpToInt() local
2792 SDValue Exp00 = DAG.getNode(ISD::SHL, dl, ResTy, {Inp, One}); in ExpandHvxFpToInt()
3278 SDValue Inp = Op.getOperand(0); in ExpandHvxResizeIntoSteps() local
3279 MVT InpTy = ty(Inp); in ExpandHvxResizeIntoSteps()
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| H A D | HexagonISelDAGToDAG.cpp | 702 SDValue Inp = N->getOperand(0); in SelectExtractSubvector() local
706 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); in SelectExtractSubvector()
714 SDValue Ext = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(N), ResTy, Inp); in SelectExtractSubvector()
960 SDValue Inp = Op, Res; in SelectInlineAsmMemoryOperand() local
968 if (SelectAddrFI(Inp, Res)) in SelectInlineAsmMemoryOperand()
971 OutOps.push_back(Inp); in SelectInlineAsmMemoryOperand()
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| H A D | HexagonPatternsHVX.td | 936 // v31:30.h = vsxt(Inp.b) ; generate masks in odd bytes in
939 // v27.b = vadd(Inp.b,v29.b) ; x + masks
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| /freebsd-14.2/contrib/llvm-project/compiler-rt/lib/fuzzer/ |
| H A D | FuzzerDriver.cpp | 895 for (auto &Inp : *Inputs) { in FuzzerDriver()
896 Printf("Loading corpus dir: %s\n", Inp.c_str()); in FuzzerDriver()
897 ReadDirToVectorOfUnits(Inp.c_str(), &InitialCorpus, nullptr, in FuzzerDriver()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13742 SDValue Inp = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, in PerformADDVecReduce() local
13744 NA = DAG.getNode(ISD::ADD, dl, MVT::i64, Inp, NA); in PerformADDVecReduce()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 48372 SDValue Inp = (i == 0) ? Node->getOperand(1) : Node->getOperand(0); in combineAndLoadToBZHI() local
48387 return DAG.getNode(ISD::AND, dl, VT, Inp, LShr); in combineAndLoadToBZHI()
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