Searched refs:InitReg (Results 1 – 3 of 3) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 1466 if (InitReg) { in phi()
1467 auto I = Phis.find({LoopReg, *InitReg}); in phi()
1482 if (!InitReg) in phi()
1488 MI->getOperand(1).setReg(*InitReg); in phi()
1489 Phis.insert({{LoopReg, *InitReg}, R}); in phi()
1491 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
1502 if (InitReg) { in phi()
1504 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
1509 .addReg(InitReg ? *InitReg : undef(RC)) in phi()
1513 if (!InitReg) in phi()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600MachineCFGStructurizer.cpp | 1287 Register InitReg = in improveSimpleJumpintoIf() local
1289 insertCondBranchBefore(LandBlk, I, R600::IF_PREDICATE_SET, InitReg, in improveSimpleJumpintoIf()
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| H A D | SIISelLowering.cpp | 4219 unsigned InitReg, unsigned ResultReg, unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
4235 .addReg(InitReg) in emitLoadM0FromVGPRLoop()
4467 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitIndirectSrc() local
4469 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg); in emitIndirectSrc()
4472 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset, in emitIndirectSrc()
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