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Searched refs:InVT (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1355 switch (getTypeAction(InVT)) { in SplitVecRes_BITCAST()
1637 if (InVT.isVector()) { in SplitVecRes_StrictFPOp()
3219 EVT InVT = Lo.getValueType(); in SplitVecOp_UnaryOp() local
3854 EVT FinalVT = InVT; in SplitVecOp_TruncateHelper()
5041 if (InVT.isVector()) in WidenVecRes_BITCAST()
5061 InVT = NInVT; in WidenVecRes_BITCAST()
5077 if (WidenVT.bitsEq(InVT)) in WidenVecRes_BITCAST()
5093 if (InVT.isVector()) { in WidenVecRes_BITCAST()
5112 if (InVT.isVector()) { in WidenVecRes_BITCAST()
7337 if (InVT == NVT) in ModifyToType()
[all …]
H A DLegalizeTypesGeneric.cpp44 EVT InVT = InOp.getValueType(); in ExpandRes_BITCAST() local
48 switch (getTypeAction(InVT)) { in ExpandRes_BITCAST()
66 if (TLI.hasBigEndianPartOrdering(InVT, DL) != in ExpandRes_BITCAST()
89 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); in ExpandRes_BITCAST()
92 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT); in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
162 Align InAlign = DAG.getReducedAlign(InVT, /*UseABI=*/false); in ExpandRes_BITCAST()
165 SDValue StackPtr = DAG.CreateStackTemporary(InVT.getStoreSize(), Align); in ExpandRes_BITCAST()
H A DLegalizeIntegerTypes.cpp414 EVT InVT = InOp.getValueType(); in PromoteIntRes_BITCAST() local
420 switch (getTypeAction(InVT)) { in PromoteIntRes_BITCAST()
1233 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1240 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_SETCC()
1241 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1504 EVT InVT = InOp.getValueType(); in PromoteIntRes_TRUNCATE() local
2444 EVT InVT = Op.getValueType(); in PromoteIntOp_VECREDUCE() local
2445 EVT EltVT = InVT.getVectorElementType(); in PromoteIntOp_VECREDUCE()
2464 switch (TLI.getBooleanContents(InVT)) { in PromoteIntOp_VECREDUCE()
5565 EVT InVT = InOp0.getValueType(); in PromoteIntRes_EXTRACT_SUBVECTOR() local
[all …]
H A DDAGCombiner.cpp23040 EVT InVT = Vec.getValueType(); in reduceBuildVecToShuffle() local
23059 InVT.getVectorNumElements()) { in reduceBuildVecToShuffle()
23246 if (LegalTypes && !TLI.isTypeLegal(InVT)) in convertBuildVecZextToZext()
24530 EVT InVT = V.getValueType(); in visitEXTRACT_SUBVECTOR() local
24532 unsigned EltSize = InVT.getScalarSizeInBits(); in visitEXTRACT_SUBVECTOR()
24536 EVT EltVT = InVT.getVectorElementType(); in visitEXTRACT_SUBVECTOR()
25182 EVT InVT = Op0.getOperand(0).getValueType(); in combineShuffleOfBitcast() local
25183 if (!InVT.isVector() || in combineShuffleOfBitcast()
25192 int InLanes = InVT.getVectorNumElements(); in combineShuffleOfBitcast()
25206 if (!TLI.isShuffleMaskLegal(NewMask, InVT)) in combineShuffleOfBitcast()
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H A DSelectionDAG.cpp3648 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3649 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
3662 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3663 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
3680 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3681 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
H A DSelectionDAGBuilder.cpp11948 EVT InVT = getValue(I.getOperand(0)).getValueType(); in visitVectorInterleave() local
11957 unsigned NumElts = InVT.getVectorMinNumElements(); in visitVectorInterleave()
11965 DAG.getVTList(InVT, InVT), InVec0, InVec1); in visitVectorInterleave()
H A DLegalizeDAG.cpp2217 EVT InVT = Node->getOperand(Node->isStrictFPOpcode() ? 1 : 0).getValueType(); in ExpandArgFPLibCall() local
2218 RTLIB::Libcall LC = RTLIB::getFPLibCall(InVT.getSimpleVT(), in ExpandArgFPLibCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2497 if (ResVT == MVT::v4f32 && (InVT == MVT::v4i16 || InVT == MVT::v4i8)) in performVectorExtendToFPCombine()
2499 else if (ResVT == MVT::v2f64 && (InVT == MVT::v2i16 || InVT == MVT::v2i8)) in performVectorExtendToFPCombine()
2728 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW() local
2730 InVT = MVT::i32; in truncateVectorWithNARROW()
2734 InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits()); in truncateVectorWithNARROW()
2743 Lo = DAG.getBitcast(InVT, Lo); in truncateVectorWithNARROW()
2744 Hi = DAG.getBitcast(InVT, Hi); in truncateVectorWithNARROW()
2764 EVT InVT = In.getValueType(); in performTruncateCombine() local
2765 if (!InVT.isSimple()) in performTruncateCombine()
2773 EVT InSVT = InVT.getVectorElementType(); in performTruncateCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h276 bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT::SimpleValueType InVT) const { in MergeInTypeInfo()
277 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
279 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) const { in MergeInTypeInfo()
280 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp20154 InVT = EVT::getVectorVT(Ctx, InVT, 128 / InVT.getSizeInBits()); in truncateVectorWithPACK()
20178 InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits()); in truncateVectorWithPACK()
20457 assert((InVT.is256BitVector() || InVT.is128BitVector()) && in LowerTruncateVecI1()
20495 InVT = ExtVT; in LowerTruncateVecI1()
20521 if ((InVT == MVT::v8i64 || InVT == MVT::v16i32 || InVT == MVT::v16i64) && in LowerTRUNCATE()
31462 if (InVT == NVT) in ExtendToType()
32307 (InVT == MVT::v4i16 || InVT == MVT::v4i8)){ in ReplaceNodeResults()
32341 InVT = getTypeToTransformTo(*DAG.getContext(), InVT); in ReplaceNodeResults()
53595 if (InVT.isVector() && InVT.getScalarSizeInBits() < 32 && in combineUIntToFP()
53665 if (InVT.isVector() && InVT.getScalarSizeInBits() < 32 && in combineSIntToFP()
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H A DX86InstrAVX512.td162 X86VectorVTInfo InVT,
167 !con((ins InVT.RC:$src1), NonTiedIns),
168 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
169 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
171 (vselect_mask InVT.KRCWM:$mask, RHS,
172 (bitconvert InVT.RC:$src1)),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4048 InVT = InVT.changeVectorElementTypeToInteger(); in LowerVectorFP_TO_INT()
4258 EVT InVT = In.getValueType(); in LowerVectorINT_TO_FP() local
4837 EVT InVT = Op.getValueType(); in getSVEPredicateBitCast() local
4849 if (InVT == VT) in getSVEPredicateBitCast()
4858 if (InVT.bitsGT(VT)) in getSVEPredicateBitCast()
18995 EVT InVT = N0.getValueType(); in performVectorAddSubExtCombine() local
24493 if (!InVT.isScalableVector() || !InVT.isInteger()) in ReplaceExtractSubVectorResults()
26316 assert(InVT.isFixedLengthVector() && isTypeLegal(InVT) && in LowerFixedLengthVectorSetccToSVE()
26783 InVT.isScalableVector() && isTypeLegal(InVT) && in getSVESafeBitCast()
26789 if (InVT == VT) in getSVESafeBitCast()
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H A DAArch64ISelDAGToDAG.cpp4224 EVT InVT = N->getOperand(1).getValueType(); in trySelectCastFixedLengthToScalableVector() local
4225 if (VT.isFixedLengthVector() || InVT.isScalableVector()) in trySelectCastFixedLengthToScalableVector()
4227 if (InVT.getSizeInBits() <= 128) in trySelectCastFixedLengthToScalableVector()
4253 EVT InVT = N->getOperand(0).getValueType(); in trySelectCastScalableToFixedLengthVector() local
4254 if (VT.isScalableVector() || InVT.isFixedLengthVector()) in trySelectCastScalableToFixedLengthVector()
4263 assert(InVT.getSizeInBits().getKnownMinValue() == AArch64::SVEBitsPerBlock && in trySelectCastScalableToFixedLengthVector()
H A DSVEInstrFormats.td2801 ValueType OutVT, ValueType InVT,
2804 …def : SVE_4_Op_Imm_Pat<OutVT, op, OutVT, InVT, InVT, i32, VectorIndexH32b_timm, !cast<Instruction>…
2838 ValueType InVT, SDPatternOperator op> {
2840 def : SVE_3_Op_Pat<OutVT, op, OutVT, InVT, InVT, !cast<Instruction>(NAME)>;
8793 string asm, ValueType InVT, SDPatternOperator op> {
8795 def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, InVT, InVT, !cast<Instruction>(NAME)>;
8820 ZPRRegOp src2_ty, string asm, ValueType InVT,
8827 …def : SVE_4_Op_Imm_Pat<nxv4f32, op, nxv4f32, InVT, InVT, i32, VectorIndexS32b_timm, !cast<Instruct…
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3808 EVT InVT = In.getValueType(); in lowerBITCAST() local
3823 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3839 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
5171 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0); in getPermuteNode()
5172 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1); in getPermuteNode()
5182 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1); in getPermuteNode()
5961 EVT InVT = PackedOp.getValueType(); in lowerSIGN_EXTEND_VECTOR_INREG() local
5963 unsigned FromBits = InVT.getScalarSizeInBits(); in lowerSIGN_EXTEND_VECTOR_INREG()
5980 EVT InVT = PackedOp.getValueType(); in lowerZERO_EXTEND_VECTOR_INREG() local
5986 DAG.getSplatVector(InVT, DL, DAG.getConstant(0, DL, InVT.getScalarType())); in lowerZERO_EXTEND_VECTOR_INREG()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3112 EVT InVT = InputOp.getValueType(); in computeLogicOpInGPR() local
3113 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 : in computeLogicOpInGPR()
3114 PPC::RLDICL, dl, InVT, InputOp, in computeLogicOpInGPR()
3257 EVT InVT = LHS.getValueType(); in getCompoundZeroComparisonInGPR() local
3258 bool Is32Bit = InVT == MVT::i32; in getCompoundZeroComparisonInGPR()
3266 dl, InVT, LHS, LHS), 0); in getCompoundZeroComparisonInGPR()
5819 EVT InVT = N->getOperand(0).getValueType(); in Select() local
5820 assert((InVT == MVT::i64 || InVT == MVT::i32) && in Select()
5823 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8_rec : PPC::ANDI_rec; in Select()
5824 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue, in Select()
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H A DPPCISelLowering.cpp8657 EVT InVT = Src.getValueType(); in LowerINT_TO_FP() local
8660 isOperationCustom(Op.getOpcode(), InVT)) in LowerINT_TO_FP()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp2050 MVT InVT = V.getSimpleValueType(); in Select() local
2058 if (InVT.isFixedLengthVector()) in Select()
2059 InVT = TLI.getContainerForFixedLengthVector(InVT); in Select()
2065 InVT, SubVecContainerVT, Idx, TRI); in Select()
2076 unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(InVT); in Select()
H A DRISCVISelLowering.cpp10209 MVT InVT = Op.getOperand(0).getSimpleValueType(); in lowerFixedLengthVectorSetccToRVV() local
10210 MVT ContainerVT = getContainerForFixedLengthVector(InVT); in lowerFixedLengthVectorSetccToRVV()
10241 MVT InVT = Op1.getSimpleValueType(); in lowerVectorStrictFSetcc() local
10273 MVT ContainerInVT = InVT; in lowerVectorStrictFSetcc()
10274 if (InVT.isFixedLengthVector()) { in lowerVectorStrictFSetcc()
10275 ContainerInVT = getContainerForFixedLengthVector(InVT); in lowerVectorStrictFSetcc()
10281 auto [Mask, VL] = getDefaultVLOps(InVT, ContainerInVT, DL, DAG, Subtarget); in lowerVectorStrictFSetcc()