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Searched refs:In64BitMode (Results 1 – 25 of 29) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSNP.td21 Requires<[In64BitMode]>;
26 TB, XD, Requires<[In64BitMode]>;
35 Requires<[In64BitMode]>;
40 Requires<[In64BitMode]>;
45 Requires<[In64BitMode]>;
48 def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>;
49 … InstAlias<"pvalidate\t{%rax, %rcx, %rdx|rdx, rcx, rax|}", (PVALIDATE64)>, Requires<[In64BitMode]>;
51 def : InstAlias<"rmpupdate\t{%rax, %rcx|rcx, rax|}", (RMPUPDATE)>, Requires<[In64BitMode]>;
52 def : InstAlias<"rmpadjust\t{%rax, %rcx, %rdx|rdx, rcx, rax|}", (RMPADJUST)>, Requires<[In64BitMode…
53 def : InstAlias<"rmpquery\t{%rax, %rdx|rdx, rax|}", (RMPQUERY)>, Requires<[In64BitMode]>;
H A DX86InstrVMX.td24 Requires<[In64BitMode]>;
27 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>;
35 Requires<[In64BitMode]>;
38 EVEX, NoCD8, T_MAP4, XS, Requires<[In64BitMode]>;
58 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
64 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
70 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
76 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
H A DX86InstrControl.td26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
38 "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
44 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
125 [(brind GR64:$dst)]>, Requires<[In64BitMode]>,
324 Requires<[In64BitMode]>;
330 Requires<[In64BitMode,FavorMemIndirectCall,
337 Requires<[In64BitMode]>, NOTRACK;
393 Requires<[In64BitMode,UseIndirectThunkCalls]>;
409 Requires<[In64BitMode]>;
413 Requires<[In64BitMode]>;
[all …]
H A DX86InstrSVM.td37 Requires<[In64BitMode]>;
45 Requires<[In64BitMode]>;
53 Requires<[In64BitMode]>;
61 "invlpga", []>, TB, Requires<[In64BitMode]>;
H A DX86InstrAsmAlias.td36 Requires<[ In64BitMode ]>;
42 Requires<[ In64BitMode ]>;
95 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
116 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
119 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
157 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
162 def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>;
194 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
197 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
200 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
[all …]
H A DX86InstrSystem.td64 Requires<[In64BitMode]>;
70 Requires<[In64BitMode]>;
131 Requires<[In64BitMode]>;
138 Requires<[In64BitMode]>;
150 Requires<[In64BitMode]>;
157 Requires<[In64BitMode]>;
180 Requires<[In64BitMode]>;
322 OpSize32, Requires<[In64BitMode]>;
538 let Predicates = [HasEGPR, In64BitMode] in {
698 Requires<[In64BitMode]>;
[all …]
H A DX86InstrArithmetic.td93 let Predicates = [In64BitMode] in {
155 let Predicates = [In64BitMode] in {
310 let Predicates = [In64BitMode] in {
745 let Predicates = [In64BitMode] in
750 let Predicates = [In64BitMode] in
930 let Predicates = [In64BitMode] in
934 let Predicates = [In64BitMode] in
1023 let Predicates = [In64BitMode] in
1029 let Predicates = [In64BitMode] in
1284 let Predicates = [In64BitMode] in
[all …]
H A DX86InstrShiftRotate.td29 let Predicates = [HasNDD, In64BitMode] in {
35 let Predicates = [In64BitMode] in {
47 let Predicates = [HasNDD, In64BitMode] in {
53 let Predicates = [In64BitMode] in {
72 let Predicates = [In64BitMode] in {
91 let Predicates = [In64BitMode] in {
119 let Predicates = [In64BitMode] in {
138 let Predicates = [In64BitMode] in {
149 let Predicates = [In64BitMode] in {
429 let Predicates = [In64BitMode] in {
[all …]
H A DX86InstrExtension.td22 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
34 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
158 Sched<[WriteALU]>, Requires<[In64BitMode]>;
162 Sched<[WriteLoad]>, Requires<[In64BitMode]>;
170 Sched<[WriteALU]>, OpSize16, Requires<[In64BitMode]>;
173 Sched<[WriteALU]>, OpSize32, Requires<[In64BitMode]>;
177 Sched<[WriteLoad]>, OpSize16, Requires<[In64BitMode]>;
180 Sched<[WriteLoad]>, OpSize32, Requires<[In64BitMode]>;
H A DX86InstrMisc.td47 Requires<[In64BitMode]>;
125 Requires<[In64BitMode]>;
138 Requires<[In64BitMode]>;
204 Requires<[In64BitMode]>;
207 Requires<[In64BitMode]>;
312 Requires<[In64BitMode]>;
327 Requires<[In64BitMode]>;
341 Requires<[In64BitMode]>;
352 Requires<[In64BitMode]>;
679 Requires<[In64BitMode]>;
[all …]
H A DX86InstrAMX.td18 let Predicates = [HasAMXTILE, HasEGPR, In64BitMode] in {
52 let Predicates = [HasAMXTILE, In64BitMode] in {
98 let Predicates = [HasAMXINT8, In64BitMode] in {
170 let Predicates = [HasAMXBF16, In64BitMode] in {
200 let Predicates = [HasAMXFP16, In64BitMode] in {
229 let Predicates = [HasAMXCOMPLEX, In64BitMode] in {
H A DX86InstrTDX.td18 let SchedRW = [WriteSystem], Predicates = [In64BitMode] in {
H A DX86InstrRAOINT.td35 let Predicates = [HasRAOINT, In64BitMode] in
H A DX86InstrCompiler.td118 Requires<[In64BitMode]>;
135 Requires<[In64BitMode]>;
161 Requires<[In64BitMode]>;
216 Requires<[In64BitMode]>;
225 Requires<[In64BitMode]>;
533 Requires<[In64BitMode]>;
841 let Predicates = [UseIncDec, In64BitMode] in {
1684 Requires<[In64BitMode]>;
1687 Requires<[In64BitMode]>;
1752 Requires<[In64BitMode]>;
[all …]
H A DX86MCInstLower.cpp403 bool In64BitMode = AsmPrinter.getSubtarget().is64Bit(); in Lower() local
407 X86::optimizeMOVSX(OutMI) || X86::optimizeINCDEC(OutMI, In64BitMode) || in Lower()
408 X86::optimizeMOV(OutMI, In64BitMode) || in Lower()
466 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX; in Lower()
496 if (In64BitMode) in Lower()
H A DX86InstrPredicates.td193 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
H A DX86InstrFPStack.td673 TB, Requires<[HasFXSR, In64BitMode]>;
682 TB, Requires<[HasFXSR, In64BitMode]>;
H A DX86InstrMMX.td554 let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
H A DX86InstrSSE.td4073 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4086 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4977 TB, Requires<[HasSSE3, In64BitMode]>;
4985 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
4990 Requires<[In64BitMode]>;
6691 let Predicates = [HasCRC32, HasEGPR, In64BitMode], OpMap = T_MAP4, OpEnc = EncEVEX in {
6770 let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode] in {
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.h23 bool optimizeINCDEC(MCInst &MI, bool In64BitMode);
24 bool optimizeMOV(MCInst &MI, bool In64BitMode);
H A DX86EncodingOptimization.cpp288 bool X86::optimizeINCDEC(MCInst &MI, bool In64BitMode) { in optimizeINCDEC() argument
289 if (In64BitMode) in optimizeINCDEC()
314 bool X86::optimizeMOV(MCInst &MI, bool In64BitMode) { in optimizeMOV() argument
317 if (In64BitMode) in optimizeMOV()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td84 Requires<[In64BitMode]>;
88 Requires<[In64BitMode]>;
92 Requires<[In64BitMode]>;
95 Requires<[In64BitMode]>;
169 Requires<[In64BitMode]>;
173 Requires<[In64BitMode]>;
176 Requires<[In64BitMode]>;
221 Requires<[In64BitMode]>;
231 Requires<[In64BitMode]>;
452 Requires<[In64BitMode]>;
[all …]
H A DPPCInstrVSX.td1296 Requires<[In64BitMode]>;
1302 Requires<[In64BitMode]>;
1314 Requires<[In64BitMode]>;
1320 Requires<[In64BitMode]>;
1347 []>, Requires<[In64BitMode]>;
1351 []>, Requires<[In64BitMode]>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrFPU.td105 // S64 - single precision in 32 64bit fp registers (In64BitMode)
107 // D64 - double precision in 32 64bit fp registers (In64BitMode)
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td1628 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1633 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;

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