| /freebsd-14.2/sys/contrib/device-tree/src/arm/ |
| H A D | imx6qdl-dhcom-picoitx.dtsi | 29 "", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "",
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| H A D | imx6ull-dhcom-picoitx.dts | 76 "DHCOM-A", "DHCOM-B", "PicoITX-In2", "PicoITX-Out2",
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| H A D | stm32mp15xx-dhcom-picoitx.dtsi | 73 gpio-line-names = "PicoITX-In2", "", "", "",
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| H A D | imx6ull-dhcom-drc02.dts | 35 "", "", "", "DRC02-In2",
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| H A D | stm32mp15xx-dhcom-drc02.dtsi | 54 "DRC02-In2", "", "", "",
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| H A D | imx6qdl-dhcom-drc02.dtsi | 48 "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
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| H A D | imx6dl-eckelmann-ci4x10.dts | 149 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 44 const APInt &In2, bool IsSigned = false) { in addWithOverflow() argument
47 Result = In1.sadd_ov(In2, Overflow); in addWithOverflow()
49 Result = In1.uadd_ov(In2, Overflow); in addWithOverflow()
57 const APInt &In2, bool IsSigned = false) { in subWithOverflow() argument
60 Result = In1.ssub_ov(In2, Overflow); in subWithOverflow()
62 Result = In1.usub_ov(In2, Overflow); in subWithOverflow()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 5030 SDValue In1, In2, In3, In4; in ExpandIntRes_FunnelShift() local
5032 GetExpandedInteger(N->getOperand(1), In1, In2); in ExpandIntRes_FunnelShift()
5053 SDValue Select1 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In1, In2); in ExpandIntRes_FunnelShift()
5054 SDValue Select2 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In2, In3); in ExpandIntRes_FunnelShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 15525 SDValue In2 = N->getOperand(1); in PerformDAGCombine() local
15528 if (!In2.hasOneUse()) in PerformDAGCombine()
15530 if (In2.getOpcode() != ISD::FP_EXTEND && in PerformDAGCombine()
15531 (In2.getOpcode() != ISD::FP_ROUND || In2.getConstantOperandVal(1) != 0)) in PerformDAGCombine()
15533 In2 = In2.getOperand(0); in PerformDAGCombine()
15534 if (In2.getOpcode() != ISD::FNEG) in PerformDAGCombine()
15537 SDValue NewFPExtRound = DAG.getFPExtendOrRound(In2.getOperand(0), DL, VT); in PerformDAGCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 9027 SDValue In2 = Op.getOperand(1); in LowerFCOPYSIGN() local
9028 EVT SrcVT = In2.getValueType(); in LowerFCOPYSIGN()
9031 In2 = DAG.getFPExtendOrRound(In2, DL, VT); in LowerFCOPYSIGN()
9042 In2 = convertToScalableVector(DAG, ContainerVT, In2); in LowerFCOPYSIGN()
9044 SDValue Res = DAG.getNode(ISD::FCOPYSIGN, DL, ContainerVT, In1, In2); in LowerFCOPYSIGN()
9062 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In2); in LowerFCOPYSIGN()
9065 VecVal2 = BitCast(VecVT, In2, DAG); in LowerFCOPYSIGN()
23600 SDValue In2 = N->getOperand(2); in performBSPExpandForSVE() local
23604 SDValue SelInv = DAG.getNode(ISD::AND, DL, VT, InvMask, In2); in performBSPExpandForSVE()
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