| /freebsd-14.2/sys/contrib/device-tree/src/arm/ |
| H A D | imx6qdl-dhcom-picoitx.dtsi | 37 "", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H",
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| H A D | imx6ull-dhcom-picoitx.dts | 77 "PicoITX-In1", "", "", "PicoITX-Out1",
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| H A D | stm32mp15xx-dhcom-picoitx.dtsi | 60 "", "", "PicoITX-In1", "",
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| H A D | imx6ull-dhcom-drc02.dts | 71 "DRC02-In1", "DHCOM-H", "", "",
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| H A D | stm32mp15xx-dhcom-drc02.dtsi | 52 gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I",
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| H A D | imx6qdl-dhcom-drc02.dtsi | 43 "", "", "", "DRC02-In1", "", "", "", "";
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| H A D | imx6dl-eckelmann-ci4x10.dts | 148 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 43 static bool addWithOverflow(APInt &Result, const APInt &In1, in addWithOverflow() argument
47 Result = In1.sadd_ov(In2, Overflow); in addWithOverflow()
49 Result = In1.uadd_ov(In2, Overflow); in addWithOverflow()
56 static bool subWithOverflow(APInt &Result, const APInt &In1, in subWithOverflow() argument
60 Result = In1.ssub_ov(In2, Overflow); in subWithOverflow()
62 Result = In1.usub_ov(In2, Overflow); in subWithOverflow()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 5030 SDValue In1, In2, In3, In4; in ExpandIntRes_FunnelShift() local
5032 GetExpandedInteger(N->getOperand(1), In1, In2); in ExpandIntRes_FunnelShift()
5033 EVT HalfVT = In1.getValueType(); in ExpandIntRes_FunnelShift()
5053 SDValue Select1 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In1, In2); in ExpandIntRes_FunnelShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 9026 SDValue In1 = Op.getOperand(0); in LowerFCOPYSIGN() local
9041 In1 = convertToScalableVector(DAG, ContainerVT, In1); in LowerFCOPYSIGN()
9044 SDValue Res = DAG.getNode(ISD::FCOPYSIGN, DL, ContainerVT, In1, In2); in LowerFCOPYSIGN()
9060 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In1); in LowerFCOPYSIGN()
9064 VecVal1 = BitCast(VecVT, In1, DAG); in LowerFCOPYSIGN()
9084 unsigned BitWidth = In1.getScalarValueSizeInBits(); in LowerFCOPYSIGN()
23599 SDValue In1 = N->getOperand(1); in performBSPExpandForSVE() local
23603 SDValue Sel = DAG.getNode(ISD::AND, DL, VT, Mask, In1); in performBSPExpandForSVE()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 9591 Value *In1 = PHI1->getIncomingValue(I); in isGatherShuffledSingleRegisterEntry() local
9592 if (isConstant(In) && isConstant(In1)) in isGatherShuffledSingleRegisterEntry()
9594 if (!getSameOpcode({In, In1}, *TLI).getOpcode()) in isGatherShuffledSingleRegisterEntry()
9597 cast<Instruction>(In1)->getParent()) in isGatherShuffledSingleRegisterEntry()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 54222 SDValue In0, In1; in matchPMADDWD_2() local
54261 In1 = N01In; in matchPMADDWD_2()
54266 In1.getValueSizeInBits() < VT.getSizeInBits()) in matchPMADDWD_2()
54275 if (In0 != N00In || In1 != N01In || In0 != N10In || In1 != N11In) in matchPMADDWD_2()
54298 if (OutVT16.bitsLT(In1.getValueType())) { in matchPMADDWD_2()
54299 In1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT16, In1, in matchPMADDWD_2()
54302 return SplitOpsAndApply(DAG, Subtarget, DL, VT, { In0, In1 }, in matchPMADDWD_2()
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