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Searched refs:In0 (Results 1 – 3 of 3) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoopVectorizationLegality.cpp1200 Value *In0 = const_cast<Value *>(V); in isInductionPhi() local
1201 PHINode *PN = dyn_cast_or_null<PHINode>(In0); in isInductionPhi()
H A DVPlanRecipes.cpp1374 Value *In0 = State.get(getIncomingValue(In), Part); in execute() local
1376 Entry[Part] = In0; // Initialize with the first incoming value. in execute()
1382 State.Builder.CreateSelect(Cond, In0, Entry[Part], "predphi"); in execute()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp54222 SDValue In0, In1; in matchPMADDWD_2() local
54259 if (!In0) { in matchPMADDWD_2()
54260 In0 = N00In; in matchPMADDWD_2()
54265 if (In0.getValueSizeInBits() < VT.getSizeInBits() || in matchPMADDWD_2()
54271 if (In0 != N00In) in matchPMADDWD_2()
54273 if (In0 != N10In) in matchPMADDWD_2()
54275 if (In0 != N00In || In1 != N01In || In0 != N10In || In1 != N11In) in matchPMADDWD_2()
54294 if (OutVT16.bitsLT(In0.getValueType())) { in matchPMADDWD_2()
54295 In0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT16, In0, in matchPMADDWD_2()
54302 return SplitOpsAndApply(DAG, Subtarget, DL, VT, { In0, In1 }, in matchPMADDWD_2()