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Searched refs:ImplicitDefine (Results 1 – 25 of 32) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp190 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
758 .addReg(ScratchRsrcReg, RegState::ImplicitDefine) in emitEntryFunctionScratchRsrcRegSetup()
792 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
807 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
818 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
822 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
827 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
831 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
858 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
862 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
H A DSIRegisterInfo.cpp214 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
231 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
1574 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1617 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1671 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1802 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillSGPR()
1901 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1934 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
2015 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillEmergencySGPR()
H A DSILowerControlFlow.cpp239 .addReg(Exec, RegState::ImplicitDefine); in emitIf()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp229 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
666 RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
H A DSystemZShortenInst.cpp148 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
H A DSystemZFrameLowering.cpp435 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
1191 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
H A DSystemZInstrInfo.cpp241 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h64 ImplicitDefine = Implicit | Define, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2172 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2195 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2254 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
2257 .addReg(PPC::RM, RegState::ImplicitDefine); in PredicateInstruction()
2808 .addReg(CRReg, RegState::ImplicitDefine); in optimizeCmpPostRA()
3269 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kFrameLowering.cpp889 I.addReg(Info.getReg(), RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
H A DM68kInstrInfo.cpp539 .addReg(Reg, RegState::ImplicitDefine) in ExpandMOVEM()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1110 .addDef(Hexagon::R29, RegState::ImplicitDefine) in expandPostRAPseudo()
1111 .addDef(Hexagon::R30, RegState::ImplicitDefine) in expandPostRAPseudo()
1112 .addDef(Hexagon::R14, RegState::ImplicitDefine) in expandPostRAPseudo()
1113 .addDef(Hexagon::R15, RegState::ImplicitDefine) in expandPostRAPseudo()
1114 .addDef(Hexagon::R28, RegState::ImplicitDefine); in expandPostRAPseudo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp246 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
H A DARMExpandPseudoInsts.cpp662 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
830 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
2783 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
H A DARMFrameLowering.cpp1929 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
1946 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
H A DARMBaseInstrInfo.cpp1448 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1494 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1524 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1549 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
H A DARMLoadStoreOptimizer.cpp960 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp2133 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2134 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
H A DMipsSEInstrInfo.cpp134 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp1469 PopBuilder.addDef(AllPopRegs[i], RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp1099 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp6079 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
6108 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
6190 MIB.addReg(Reg, RegState::ImplicitDefine); in expandPostRAPseudo()
7024 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
7046 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
7055 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp1631 Flags |= RegState::ImplicitDefine; in parseRegisterFlag()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2661 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in emitSjLjDispatchBlock()

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