Searched refs:ImplDef (Results 1 – 5 of 5) sorted by relevance
| /freebsd-14.2/sys/contrib/device-tree/Bindings/arm/ |
| H A D | qcom,coresight-tpdm.yaml | 12 types specified in the QPMDA spec. It covers Implementation defined ((ImplDef),
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 338 MachineOperand ImplDef = in addLinkerOpt() local
342 Pair->DefInst->addOperand(ImplDef); in addLinkerOpt()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 480 Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select() local
482 .addDef(ImplDef); in select()
485 ImplDef, MMO)) in select()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2973 SDValue ImplDef = SDValue(CurDAG->getMachineNode(X86::IMPLICIT_DEF, DL, in selectLEA64_32Addr() local
2975 Base = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, MVT::i64, ImplDef, in selectLEA64_32Addr()
2985 SDValue ImplDef = SDValue(CurDAG->getMachineNode(X86::IMPLICIT_DEF, DL, in selectLEA64_32Addr() local
2987 Index = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, MVT::i64, ImplDef, in selectLEA64_32Addr()
3926 SDValue ImplDef = SDValue( in matchBitExtract() local
3928 insertDAGNode(*CurDAG, SDValue(Node, 0), ImplDef); in matchBitExtract()
3933 MVT::i32, ImplDef, NBits, SRIdxVal), in matchBitExtract()
4904 SDValue ImplDef = SDValue(CurDAG->getMachineNode(X86::IMPLICIT_DEF, dl, in tryVPTESTM() local
4906 Src0 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src0); in tryVPTESTM()
4909 Src1 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src1); in tryVPTESTM()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2203 SDValue ImplDef = in SelectVLD() local
2205 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
3041 SDValue ImplDef = SDValue( in SelectVLDDup() local
3043 const SDValue OpsA[] = {MemAddr, Align, ImplDef, Pred, Reg0, Chain}; in SelectVLDDup()
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