| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFormats.td | 84 class ImmType<bits<4> val> {
87 def NoImm : ImmType<0>;
88 def Imm8 : ImmType<1>;
89 def Imm8PCRel : ImmType<2>;
91 def Imm16 : ImmType<4>;
92 def Imm16PCRel : ImmType<5>;
93 def Imm32 : ImmType<6>;
94 def Imm32PCRel : ImmType<7>;
95 def Imm32S : ImmType<8>;
96 def Imm64 : ImmType<9>;
[all …]
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| H A D | X86InstrUtils.td | 69 ImmType ImmT = Imm8;
73 ImmType ImmT = Imm8;
77 ImmType ImmT = Imm8;
81 ImmType ImmT = Imm8;
85 ImmType ImmT = Imm8;
131 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
159 ImmType ImmEncoding = immkind;
812 ImmType ImmT = Imm8;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrFormats.td | 79 class I_16_ZX<string op, ImmLeaf ImmType, list<dag> pattern>
81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
93 class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
96 [(set GPR:$rz, ImmType:$imm16)]> {
197 class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
200 [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
264 class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
267 (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
471 class I_5_X<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
474 (outs CARRY:$ca), (ins GPR:$rx, ImmType:$imm5),
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoZvk.td | 286 multiclass VPseudoVALU_VI_NoMask_Zvk<Operand ImmType = simm5, string Constraint = ""> {
292 defm _VI : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass, ImmType, m,
298 multiclass VPseudoVALU_VI_NoMaskTU_Zvk<Operand ImmType = uimm5, string Constraint = ""> {
304 defm _VI : VPseudoBinaryNoMask<m.vrclass, m.vrclass, ImmType, m,
831 list<VTypeInfo> vtilist, Operand ImmType = uimm6>
834 VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
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| H A D | RISCVInstrInfoVPseudos.td | 2354 multiclass VPseudoBinaryW_VI<Operand ImmType, LMULInfo m> {
2696 defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2718 defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2733 defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2761 defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
2976 multiclass VPseudoVALU_VX_VI<Operand ImmType = simm5> {
2982 defm "" : VPseudoBinaryV_VI<ImmType, m>,
3001 defm "" : VPseudoBinaryW_VI<ImmType, m>;
3413 defm "" : VPseudoVSLDV_VI<ImmType, m, Constraint>,
6063 ImmLeaf ImmType> {
[all …]
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| H A D | RISCVInstrInfoVSDPatterns.td | 160 Operand ImmType = simm5>
167 !cast<ComplexPattern>(SplatPat#_#ImmType),
168 ImmType>;
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| H A D | RISCVInstrInfo.td | 1174 class PatGprImm<SDPatternOperator OpNode, RVInst Inst, ImmLeaf ImmType,
1176 : Pat<(vt (OpNode (vt GPR:$rs1), ImmType:$imm)),
1177 (Inst GPR:$rs1, ImmType:$imm)>;
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| H A D | RISCVInstrInfoVVLPatterns.td | 781 Operand ImmType = simm5>
788 !cast<ComplexPattern>(SplatPat#_#ImmType),
789 ImmType>;
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 374 MVT ImmType);
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 2009 (ins Int32Regs:$src, ImmType:$b),
2012 (ins Int64Regs:$src, ImmType:$b),
2018 Operand ImmType, SDNode Imm, ValueType ImmTy,
2044 (ins Int32Regs:$src, ImmType:$b, ImmType:$c),
2047 (ins Int64Regs:$src, ImmType:$b, ImmType:$c),
2064 regT, regclass, ImmType, Imm, ImmTy, Preds>;
2078 regT, regclass, ImmType, Imm, ImmTy, Preds>;
2103 regT, regclass, ImmType, Imm, ImmTy,
2106 regT, regclass, ImmType, Imm, ImmTy,
2115 regT, regclass, ImmType, Imm, ImmTy,
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1941 uint64_t Imm, MVT ImmType) { in fastEmit_ri_() argument
1962 Register MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm); in fastEmit_ri_()
|