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/freebsd-14.2/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DExecuteStage.cpp81 InstRef IR = HWS.select(); in issueReadyInstructions() local
82 while (IR) { in issueReadyInstructions()
87 IR = HWS.select(); in issueReadyInstructions()
106 for (InstRef &IR : Executed) { in cycleStart()
117 notifyInstructionReady(IR); in cycleStart()
177 notifyInstructionPending(IR); in handleInstructionEliminated()
178 notifyInstructionReady(IR); in handleInstructionEliminated()
191 HWS.instructionCheck(IR); in execute()
213 notifyInstructionPending(IR); in execute()
216 notifyInstructionReady(IR); in execute()
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H A DInOrderIssueStage.cpp25 IR.invalidate(); in clear()
31 IR = Inst; in update()
124 if (hasResourceHazard(RM, IR)) { in canExecute()
129 if (IR.getInstruction()->isMemOp() && !LSU.isReady(IR)) { in canExecute()
217 if (!canExecute(IR)) { in tryIssue()
238 LSU.onInstructionIssued(IR); in tryIssue()
250 CarriedOver = IR; in tryIssue()
268 retireInstruction(IR); in tryIssue()
272 IssuedInst.push_back(IR); in tryIssue()
286 InstRef &IR = *I; in updateIssuedInst() local
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H A DDispatchStage.cpp72 bool CanDispatch = checkRCU(IR); in canDispatch()
73 CanDispatch &= checkPRF(IR); in canDispatch()
74 CanDispatch &= checkNextStage(IR); in canDispatch()
78 Error DispatchStage::dispatch(InstRef IR) { in dispatch() argument
80 Instruction &IS = *IR.getInstruction(); in dispatch()
86 CarriedOver = IR; in dispatch()
123 unsigned RCUTokenID = RCU.dispatch(IR); in dispatch()
131 return moveToTheNextStage(IR); in dispatch()
171 return canDispatch(IR); in isAvailable()
174 Error DispatchStage::execute(InstRef &IR) { in execute() argument
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H A DMicroOpQueueStage.cpp22 InstRef IR = Buffer[CurrentInstructionSlotIdx]; in moveInstructions() local
23 while (IR && checkNextStage(IR)) { in moveInstructions()
24 if (llvm::Error Val = moveToTheNextStage(IR)) in moveInstructions()
28 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR); in moveInstructions()
32 IR = Buffer[CurrentInstructionSlotIdx]; in moveInstructions()
46 Error MicroOpQueueStage::execute(InstRef &IR) { in execute() argument
47 Buffer[NextAvailableSlotIdx] = IR; in execute()
48 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR); in execute()
H A DRetireStage.cpp36 notifyInstructionRetired(Current.IR); in cycleStart()
49 llvm::Error RetireStage::execute(InstRef &IR) { in execute() argument
50 Instruction &IS = *IR.getInstruction(); in execute()
60 void RetireStage::notifyInstructionRetired(const InstRef &IR) const { in notifyInstructionRetired()
61 LLVM_DEBUG(llvm::dbgs() << "[E] Instruction Retired: #" << IR << '\n'); in notifyInstructionRetired()
63 const Instruction &Inst = *IR.getInstruction(); in notifyInstructionRetired()
67 LSU.onInstructionRetired(IR); in notifyInstructionRetired()
71 notifyEvent<HWInstructionEvent>(HWInstructionRetiredEvent(IR, FreedRegs)); in notifyInstructionRetired()
/freebsd-14.2/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp71 InstRef &IR, in issueInstructionImpl() argument
100 InstRef &IR, in issueInstruction() argument
124 InstRef &IR = *I; in promoteToReadySet() local
125 if (!IR) in promoteToReadySet()
146 IR.invalidate(); in promoteToReadySet()
160 InstRef &IR = *I; in promoteToPendingSet() local
161 if (!IR) in promoteToPendingSet()
183 IR.invalidate(); in promoteToPendingSet()
215 return IR; in select()
222 if (!IR) in updateIssuedSet()
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H A DLSUnit.cpp69 unsigned LSUnit::dispatch(const InstRef &IR) { in dispatch() argument
70 const Instruction &IS = *IR.getInstruction(); in dispatch()
197 const Instruction &IS = *IR.getInstruction(); in isAvailable()
205 void LSUnitBase::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted() argument
206 unsigned GroupID = IR.getInstruction()->getLSUTokenID(); in onInstructionExecuted()
209 It->second->onInstructionExecuted(IR); in onInstructionExecuted()
214 void LSUnitBase::onInstructionRetired(const InstRef &IR) { in onInstructionRetired() argument
215 const Instruction &IS = *IR.getInstruction(); in onInstructionRetired()
233 void LSUnit::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted() argument
234 const Instruction &IS = *IR.getInstruction(); in onInstructionExecuted()
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H A DRetireControlUnit.cpp43 unsigned RetireControlUnit::dispatch(const InstRef &IR) { in dispatch() argument
44 const Instruction &Inst = *IR.getInstruction(); in dispatch()
49 Queue[NextAvailableSlotIdx] = {IR, Entries, false}; in dispatch()
61 const Instruction *Inst = Current.IR.getInstruction(); in getCurrentToken()
79 Current.IR.getInstruction()->retire(); in consumeCurrentToken()
90 assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!"); in onInstructionExecuted()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h121 CriticalPredecessor.IID = IR.getSourceIndex(); in onGroupIssued()
132 void onInstructionIssued(const InstRef &IR) { in onInstructionIssued() argument
137 const Instruction &IS = *IR.getInstruction(); in onInstructionIssued()
141 CriticalMemoryInstruction = IR; in onInstructionIssued()
143 CriticalMemoryInstruction = IR; in onInstructionIssued()
160 void onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted() argument
273 bool isReady(const InstRef &IR) const { in isReady() argument
281 bool isPending(const InstRef &IR) const { in isPending() argument
289 bool isWaiting(const InstRef &IR) const { in isWaiting() argument
327 Groups[GroupID]->onInstructionIssued(IR); in onInstructionIssued()
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H A DScheduler.h138 InstRef &IR,
186 Status isAvailable(const InstRef &IR);
198 bool dispatch(InstRef &IR);
204 InstRef &IR,
211 bool mustIssueImmediately(const InstRef &IR) const;
270 void instructionCheck(const InstRef &IR) const { in instructionCheck() argument
271 assert(!is_contained(WaitSet, IR) && "Already in the wait set!"); in instructionCheck()
272 assert(!is_contained(ReadySet, IR) && "Already in the ready set!"); in instructionCheck()
273 assert(!is_contained(IssuedSet, IR) && "Already executing!"); in instructionCheck()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DPassManagerImpl.h36 AnalysisManager<IRUnitT, ExtraArgTs...>::clear(IRUnitT &IR, in clear() argument
41 auto ResultsListI = AnalysisResultLists.find(&IR); in clear()
46 AnalysisResults.erase({IDAndResult.first, &IR}); in clear()
55 AnalysisKey *ID, IRUnitT &IR, ExtraArgTs... ExtraArgs) { in getResultImpl() argument
69 PI.runBeforeAnalysis(P, IR); in getResultImpl()
75 PI.runAfterAnalysis(P, IR); in getResultImpl()
79 RI = AnalysisResults.find({ID, &IR}); in getResultImpl()
90 IRUnitT &IR, const PreservedAnalyses &PA) { in invalidate() argument
135 PI->runAnalysisInvalidated(this->lookUpPass(ID), IR); in invalidate()
138 AnalysisResults.erase({ID, &IR}); in invalidate()
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H A DPassManager.h76 IR.convertToNewDbgValues(); in doConvertDbgInfoToNew()
80 IR.convertFromNewDbgValues(); in doConvertDebugInfoToOld()
462 PassT, IRUnitT>)(AM, IR, Args, in getAnalysisResult()
534 doConvertDbgInfoToNew(IR); in run()
547 AM.invalidate(IR, PassPA); in run()
559 doConvertDebugInfoToOld(IR); in run()
723 return invalidateImpl<>(ID, IR, PA); in invalidate()
739 auto RI = Results.find({ID, &IR}); in invalidateImpl()
911 AnalysisResults.find({ID, &IR}); in getCachedResultImpl()
1360 if (!PI.runBeforePass<IRUnitT>(P, IR)) in run()
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H A DPassInstrumentation.h229 bool runBeforePass(const PassT &Pass, const IRUnitT &IR) const { in runBeforePass() argument
236 ShouldRun &= C(Pass.name(), llvm::Any(&IR)); in runBeforePass()
241 C(Pass.name(), llvm::Any(&IR)); in runBeforePass()
244 C(Pass.name(), llvm::Any(&IR)); in runBeforePass()
254 void runAfterPass(const PassT &Pass, const IRUnitT &IR, in runAfterPass() argument
258 C(Pass.name(), llvm::Any(&IR), PA); in runAfterPass()
275 void runBeforeAnalysis(const PassT &Analysis, const IRUnitT &IR) const { in runBeforeAnalysis() argument
278 C(Analysis.name(), llvm::Any(&IR)); in runBeforeAnalysis()
284 void runAfterAnalysis(const PassT &Analysis, const IRUnitT &IR) const { in runAfterAnalysis() argument
287 C(Analysis.name(), llvm::Any(&IR)); in runAfterAnalysis()
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H A DPassManagerInternal.h47 virtual PreservedAnalyses run(IRUnitT &IR, AnalysisManagerT &AM,
87 PreservedAnalysesT run(IRUnitT &IR, AnalysisManagerT &AM, in run()
89 return Pass.run(IR, AM, ExtraArgs...); in run()
142 virtual bool invalidate(IRUnitT &IR, const PreservedAnalysesT &PA,
258 bool invalidate(IRUnitT &IR, const PreservedAnalysesT &PA,
260 return Result.invalidate(IR, PA, Inv);
280 run(IRUnitT &IR, AnalysisManager<IRUnitT, ExtraArgTs...> &AM,
322 run(IRUnitT &IR, AnalysisManager<IRUnitT, ExtraArgTs...> &AM,
325 Pass.run(IR, AM, std::forward<ExtraArgTs>(ExtraArgs)...));
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h37 InstRef IR; member
45 const InstRef &getInstruction() const { return IR; } in getInstruction()
46 InstRef &getInstruction() { return IR; } in getInstruction()
48 bool isValid() const { return (bool)IR; } in isValid()
88 bool canExecute(const InstRef &IR);
91 Error tryIssue(InstRef &IR);
103 void notifyInstructionIssued(const InstRef &IR,
107 void notifyInstructionExecuted(const InstRef &IR);
108 void notifyInstructionRetired(const InstRef &IR,
112 void retireInstruction(InstRef &IR);
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H A DExecuteStage.h37 Error issueInstruction(InstRef &IR);
44 Error handleInstructionEliminated(InstRef &IR);
62 bool isAvailable(const InstRef &IR) const override;
73 Error execute(InstRef &IR) override;
75 void notifyInstructionIssued(const InstRef &IR,
77 void notifyInstructionExecuted(const InstRef &IR) const;
78 void notifyInstructionPending(const InstRef &IR) const;
79 void notifyInstructionReady(const InstRef &IR) const;
83 void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
H A DDispatchStage.h58 bool checkRCU(const InstRef &IR) const;
59 bool checkPRF(const InstRef &IR) const;
60 bool canDispatch(const InstRef &IR) const;
61 Error dispatch(InstRef IR);
63 void notifyInstructionDispatched(const InstRef &IR,
72 bool isAvailable(const InstRef &IR) const override;
78 Error execute(InstRef &IR) override;
H A DStage.h42 virtual bool isAvailable(const InstRef &IR) const { return true; } in isAvailable() argument
58 virtual Error execute(InstRef &IR) = 0;
65 bool checkNextStage(const InstRef &IR) const { in checkNextStage() argument
66 return NextInSequence && NextInSequence->isAvailable(IR); in checkNextStage()
73 Error moveToTheNextStage(InstRef &IR) { in moveToTheNextStage() argument
74 assert(checkNextStage(IR) && "Next stage is not ready!"); in moveToTheNextStage()
75 return NextInSequence->execute(IR); in moveToTheNextStage()
H A DMicroOpQueueStage.h54 unsigned getNormalizedOpcodes(const InstRef &IR) const { in getNormalizedOpcodes() argument
57 IR.getInstruction()->getDesc().NumMicroOps); in getNormalizedOpcodes()
67 bool isAvailable(const InstRef &IR) const override { in isAvailable() argument
70 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR); in isAvailable()
80 Error execute(InstRef &IR) override;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Passes/
H A DStandardInstrumentations.cpp219 if (unwrapIR<Module>(IR)) in getIRName()
253 bool shouldPrintIR(Any IR) { in shouldPrintIR() argument
271 if (!shouldPrintIR(IR)) in unwrapAndPrint()
362 handleInitialIR(IR); in saveIRBeforePass()
486 unwrapAndPrint(OS, IR); in generateIRRepresentation()
710 if (unwrapIR<Module>(IR)) { in getIRFileDisplayName()
812 if (!shouldPrintIR(IR)) in printBeforePass()
949 [this](StringRef P, Any IR) { this->printBeforePass(P, IR); }); in registerCallbacks() argument
966 [this](StringRef P, Any IR) { return this->shouldRun(P, IR); }); in registerCallbacks() argument
1482 [this](StringRef P, Any IR) { this->runBeforePass(P, IR); }); in registerCallbacks() argument
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/
H A DHWEventListener.h53 : Type(type), IR(Inst) {} in HWInstructionEvent()
59 const InstRef &IR; variable
70 HWInstructionIssuedEvent(const InstRef &IR, ArrayRef<ResourceUse> UR) in HWInstructionIssuedEvent() argument
71 : HWInstructionEvent(HWInstructionEvent::Issued, IR), UsedResources(UR) {} in HWInstructionIssuedEvent()
78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
80 : HWInstructionEvent(HWInstructionEvent::Dispatched, IR), in HWInstructionDispatchedEvent()
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
100 : HWInstructionEvent(HWInstructionEvent::Retired, IR), in HWInstructionRetiredEvent()
125 HWStallEvent(unsigned type, const InstRef &Inst) : Type(type), IR(Inst) {} in HWStallEvent()
131 const InstRef &IR; variable
/freebsd-14.2/share/i18n/csmapper/GB/
H A Dmapper.dir.GB.src12 ISO-IR-165EXT/UCS mapper_std GB/ISO-IR-165EXT%UCS.mps
19 ISO-IR-165/UCS mapper_parallel ISO-IR-165EXT/UCS,GB2312/UCS
28 UCS/ISO-IR-165EXT mapper_std GB/UCS%ISO-IR-165EXT.mps
36 UCS/ISO-IR-165 mapper_parallel UCS/ISO-IR-165EXT,UCS/GB2312
/freebsd-14.2/contrib/llvm-project/llvm/include/
H A Dmodule.install.modulemap15 textual header "llvm/IR/Attributes.gen"
16 textual header "llvm/IR/Attributes.inc"
20 textual header "llvm/IR/Intrinsics.gen"
21 textual header "llvm/IR/Intrinsics.inc"
25 textual header "llvm/IR/IntrinsicEnums.inc"
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Passes/
H A DStandardInstrumentations.h61 void printBeforePass(StringRef PassID, Any IR);
62 void printAfterPass(StringRef PassID, Any IR);
70 void pushPassRunDescriptor(StringRef PassID, Any IR,
91 bool shouldRun(StringRef PassID, Any IR);
99 bool shouldRun(StringRef PassName, Any IR);
211 virtual void handleInitialIR(Any IR) = 0;
245 void handleInitialIR(Any IR) override;
291 void handleInitialIR(Any IR) override;
404 static void analyzeIR(Any IR, IRDataT<T> &Data);
468 void runBeforePass(StringRef PassID, Any IR);
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/freebsd-14.2/sys/contrib/device-tree/Bindings/media/
H A Dtango-ir.txt1 Sigma Designs Tango IR NEC/RC-5/RC-6 decoder (SMP86xx and SMP87xx)
7 - interrupts: spec for IR IRQ
8 - clocks: spec for IR clock (typically the crystal oscillator)

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