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Searched refs:INSERT_SUBVECTOR (Results 1 – 23 of 23) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h559 INSERT_SUBVECTOR, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1473 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
3288 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Lo, Idx); in SplitVecOp_INSERT_SUBVECTOR()
3290 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, FirstInsertion, Hi, in SplitVecOp_INSERT_SUBVECTOR()
4078 case ISD::INSERT_SUBVECTOR: in WidenVectorResult()
4599 Oper = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in WidenVecRes_StrictFP()
4704 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
4707 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
6177 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT, in WidenVecOp_EXTEND()
6445 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, InVec, SubVec, in WidenVecOp_INSERT_SUBVECTOR()
6810 Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVT, Op, SplatNeutral, in WidenVecOp_VECREDUCE()
[all …]
H A DSelectionDAGDumper.cpp304 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
H A DLegalizeVectorOps.cpp1242 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1301 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandZERO_EXTEND_VECTOR_INREG()
H A DDAGCombiner.cpp2046 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
22791 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
22819 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
24008 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
24561 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
25579 TLI.isOperationLegalOrCustom(ISD::INSERT_SUBVECTOR, VT)) { in visitVECTOR_SHUFFLE()
26145 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
26194 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26203 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
26206 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0, in visitINSERT_SUBVECTOR()
[all …]
H A DLegalizeIntegerTypes.cpp117 case ISD::INSERT_SUBVECTOR: in PromoteIntegerResult()
1824 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break; in PromoteIntegerOperand()
5653 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx); in PromoteIntRes_INSERT_SUBVECTOR()
5905 SDValue Ext = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, PromVT, V0, V1, Idx); in PromoteIntOp_INSERT_SUBVECTOR()
5931 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DSelectionDAG.cpp3196 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
4747 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
5017 case ISD::INSERT_SUBVECTOR: in canCreateUndefOrPoison()
6971 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
7160 case ISD::INSERT_SUBVECTOR: { in getNode()
12364 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N, in WidenVector()
H A DTargetLowering.cpp864 case ISD::INSERT_SUBVECTOR: { in SimplifyMultipleUseDemandedBits()
1232 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedBits()
1403 if (Op0.getOpcode() == ISD::INSERT_SUBVECTOR && !VT.isScalableVector() && in SimplifyDemandedBits()
1418 TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, NewAnd, in SimplifyDemandedBits()
3255 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedVectorElts()
3273 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in SimplifyDemandedVectorElts()
H A DSelectionDAGBuilder.cpp670 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in widenVectorToPartType()
7683 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, in visitIntrinsicCall()
H A DLegalizeDAG.cpp3391 case ISD::INSERT_SUBVECTOR: in ExpandNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1253 (Op.getOpcode() == ISD::INSERT_SUBVECTOR && in isTargetCanonicalConstantNode()
1255 Op = Op.getOperand(Op.getOpcode() == ISD::INSERT_SUBVECTOR ? 1 : 0); in isTargetCanonicalConstantNode()
H A DX86ISelLowering.cpp2437 ISD::INSERT_SUBVECTOR, in X86TargetLowering()
3931 if (N->getOpcode() == ISD::INSERT_SUBVECTOR) { in collectConcatOps()
4832 if (Op.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetConstantBitsFromNode()
5581 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetShuffleAndZeroables()
5774 case ISD::INSERT_SUBVECTOR: { in getFauxShuffleMask()
6294 if (Opcode == ISD::INSERT_SUBVECTOR) { in getShuffleScalarElt()
12406 case ISD::INSERT_SUBVECTOR: { in lowerShuffleAsBroadcast()
14847 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV2X128Shuffle()
16534 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV4X128Shuffle()
55325 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR && in combineINSERT_SUBVECTOR()
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H A DX86ISelDAGToDAG.cpp766 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR && in IsProfitableToFold()
999 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
1002 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
1027 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
1030 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp845 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
986 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
4059 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Passthru, in lowerScalarInsert()
6404 case ISD::INSERT_SUBVECTOR: in LowerOperation()
9199 InitialValue = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, M1VT, in lowerReductionSeq()
9406 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, in lowerINSERT_SUBVECTOR()
9413 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, in lowerINSERT_SUBVECTOR()
9485 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InterSubVT, in lowerINSERT_SUBVECTOR()
9922 ISD::INSERT_SUBVECTOR, DL, VecVT, Res, Lo, in lowerVECTOR_REVERSE()
10056 StoreVal = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerFixedLengthVectorStoreToRVV()
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H A DRISCVISelDAGToDAG.cpp1993 case ISD::INSERT_SUBVECTOR: { in Select()
3106 if (N.getOpcode() == ISD::INSERT_SUBVECTOR) { in findVSplat()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp133 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
232 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
389 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
3206 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1644 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1694 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3345 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1301 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1370 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1395 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1451 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1526 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
6224 case ISD::INSERT_SUBVECTOR: in LowerOperation()
21322 DAG.getNode(ISD::INSERT_SUBVECTOR, DL, NewVT, in performLOADCombine()
23612 if (Insert.getOpcode() != ISD::INSERT_SUBVECTOR) in performDupLane128Combine()
23636 DAG.getNode(ISD::INSERT_SUBVECTOR, DL, NewSubvecVT, in performDupLane128Combine()
23905 case ISD::INSERT_SUBVECTOR: in PerformDAGCombine()
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H A DAArch64ISelDAGToDAG.cpp4214 assert(N->getOpcode() == ISD::INSERT_SUBVECTOR && "Invalid Node!"); in trySelectCastFixedLengthToScalableVector()
4432 case ISD::INSERT_SUBVECTOR: { in Select()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td757 def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
763 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp337 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
440 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
444 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
630 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
5559 case ISD::INSERT_SUBVECTOR: in LowerOperation()
H A DAMDGPUISelLowering.cpp1772 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1775 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1026 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR, in ARMTargetLowering()
18890 case ISD::INSERT_SUBVECTOR: return PerformInsertSubvectorCombine(N, DCI); in PerformDAGCombine()