| /freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenHwModes.h | 30 struct HwMode { struct
31 HwMode(Record *R);
51 const HwMode &getMode(unsigned Id) const { in getMode() argument
62 std::vector<HwMode> Modes;
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| H A D | CodeGenHwModes.cpp | 21 HwMode::HwMode(Record *R) { in HwMode() function in HwMode
40 void HwMode::dump() const { in dump()
101 for (const HwMode &M : Modes) { in dump()
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| H A D | CodeEmitterGen.cpp | 71 CodeGenTarget &Target, int HwMode = -1);
358 CodeGenTarget &Target, int HwMode) { in emitInstructionBaseValues() argument
360 if (HwMode == -1) in emitInstructionBaseValues()
363 o << " static const uint64_t InstBits_" << HWM.getMode(HwMode).Name in emitInstructionBaseValues()
379 if (EBM.hasMode(HwMode)) in emitInstructionBaseValues()
380 EncodingDef = EBM.get(HwMode); in emitInstructionBaseValues()
481 for (unsigned HwMode : HwModes) in run() local
482 emitInstructionBaseValues(o, NumberedInstructions, Target, (int)HwMode); in run()
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| H A D | RegisterBankEmitter.cpp | 95 const CodeGenRegisterClass *getRCWithLargestRegSize(unsigned HwMode) const { in getRCWithLargestRegSize()
96 return RCsWithLargestRegSize[HwMode]; in getRCWithLargestRegSize()
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| H A D | SubtargetEmitter.cpp | 1783 const HwMode &HM = CGH.getMode(M); in EmitHwModeCheck()
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| H A D | CodeGenDAGPatterns.cpp | 4460 const HwMode &HM = CGH.getMode(M); in ExpandHwModeBasedTypes()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 398 unsigned HwMode; variable
427 const unsigned *Sizes, unsigned HwMode);
591 return Sizes[RegBankID + HwMode * NumRegBanks]; in getMaximumSize()
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| H A D | TargetRegisterInfo.h | 254 unsigned HwMode; variable
774 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVRegisterBankInfo.h | 34 RISCVRegisterBankInfo(unsigned HwMode);
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| H A D | RISCVRegisterBankInfo.cpp | 74 RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode) in RISCVRegisterBankInfo() argument
75 : RISCVGenRegisterBankInfo(HwMode) {} in RISCVRegisterBankInfo()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchRegisterInfo.h | 26 LoongArchRegisterInfo(unsigned HwMode);
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| H A D | LoongArchRegisterInfo.cpp | 33 LoongArchRegisterInfo::LoongArchRegisterInfo(unsigned HwMode) in LoongArchRegisterInfo() argument
36 /*PC*/ 0, HwMode) {} in LoongArchRegisterInfo()
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| H A D | LoongArch.td | 33 def LA64 : HwMode<"+64bit", [IsLA64]>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 31 HexagonRegisterInfo(unsigned HwMode);
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| H A D | HexagonRegisterInfo.cpp | 56 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) in HexagonRegisterInfo() argument
58 0/*PC*/, HwMode) {} in HexagonRegisterInfo()
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| H A D | Hexagon.td | 163 def Hvx64: HwMode<"+hvx-length64b", [UseHVX64B]>;
164 def Hvx128: HwMode<"+hvx-length128b", [UseHVX128B]>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.h | 25 RISCVRegisterInfo(unsigned HwMode);
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| H A D | RISCVGISel.td | 60 // refers to handles both i32 and i64 based on the HwMode. Currently this LLT
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| H A D | RISCVRegisterInfo.cpp | 53 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) in RISCVRegisterInfo() argument
55 /*PC*/0, HwMode) {} in RISCVRegisterInfo()
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| H A D | RISCVRegisterInfo.td | 66 // GPR sizes change with HwMode.
67 // FIXME: Support HwMode in SubRegIndex?
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| H A D | RISCVFeatures.td | 998 def RV64 : HwMode<"+64bit", [IsRV64]>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 58 unsigned HwMode) in RegisterBankInfo() argument
60 HwMode(HwMode) { in RegisterBankInfo()
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| H A D | TargetRegisterInfo.cpp | 65 RCInfos(RCIs), RCVTLists(RCVTLists), HwMode(Mode) { in TargetRegisterInfo()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 23 class HwMode<string FS, list<Predicate> Ps> {
39 def DefaultMode : HwMode<"", []>;
46 class HwModeSelect<list<HwMode> Ms> {
47 list<HwMode> Modes = Ms;
55 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
80 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
556 // Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies
558 // to encode and decode based on HwMode.
559 class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []>
576 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty,
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