| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1043 Words[IdxW].push_back(HiHalf(W0, DAG)); in createHvxPrefixPred()
1053 Words[IdxW].push_back(HiHalf(T, DAG)); in createHvxPrefixPred()
1376 V1 = HiHalf(VecV, DAG); in insertHvxSubvectorReg()
1423 SDValue R1 = HiHalf(V, DAG); in insertHvxSubvectorReg()
2522 {HiHalf(P2, DAG), LoHalf(P1, DAG), S16}, DAG); in emitHvxMulHsV60()
2570 {HiHalf(P1, DAG), LoHalf(P1, DAG)}, DAG); in emitHvxMulLoHiV60()
2578 {HiHalf(P2, DAG), T3, S16}, DAG); in emitHvxMulLoHiV60()
2583 Hi = DAG.getNode(ISD::ADD, dl, VecTy, {HiHalf(P0, DAG), T4}); in emitHvxMulLoHiV60()
2629 SDValue Hi = HiHalf(P1, DAG); in emitHvxMulLoHiV62()
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| H A D | HexagonISelDAGToDAGHVX.cpp | 636 return OpRef(R.OpN & (Undef | Index | HiHalf)); in hi()
653 HiHalf = 0x40000000, enumerator
654 Whole = LoHalf | HiHalf,
729 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf); in print()
1191 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf); in materialize()
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| H A D | HexagonISelLowering.h | 463 SDValue HiHalf(SDValue V, SelectionDAG &DAG) const { in HiHalf() function
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| H A D | HexagonISelLowering.cpp | 2681 ExtV = Off == 0 ? LoHalf(VecV, DAG) : HiHalf(VecV, DAG); in extractVector()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1996 MachineInstr *HiHalf = in computeBase() local
2003 (void)HiHalf; in computeBase()
2004 LLVM_DEBUG(dbgs() << " "; HiHalf->dump();); in computeBase()
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| H A D | SIInstrInfo.cpp | 7687 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp() local
7702 Worklist.insert(&HiHalf); in splitScalar64BitUnaryOp()
7794 MachineInstr *HiHalf = in splitScalarSMulU64() local
7814 legalizeOperands(*HiHalf, MDT); in splitScalarSMulU64()
7860 MachineInstr *HiHalf = in splitScalarSMulPseudo() local
7878 legalizeOperands(*HiHalf, MDT); in splitScalarSMulPseudo()
7932 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp() local
7946 Worklist.insert(&HiHalf); in splitScalar64BitBinaryOp()
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| H A D | SIISelLowering.cpp | 4858 MachineInstr *HiHalf = in EmitInstrWithCustomInserter() local
4872 TII->legalizeOperands(*HiHalf); in EmitInstrWithCustomInserter()
6788 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
6792 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf); in lowerINSERT_VECTOR_ELT()
6804 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) : in lowerINSERT_VECTOR_ELT()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4861 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D() local
4878 .addDef(HiHalf) in emitLDR_D()
4886 .addUse(HiHalf); in emitLDR_D()
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