Home
last modified time | relevance | path

Searched refs:Hi (Results 1 – 25 of 163) sorted by relevance

1234567

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.h228 SDValue JoinIntegers(SDValue Lo, SDValue Hi);
237 SDValue &Lo, SDValue &Hi);
488 SDValue &Lo, SDValue &Hi);
624 SDValue &Lo, SDValue &Hi);
882 SDValue &Hi);
891 SDValue &Hi);
1082 GetSplitVector(Op, Lo, Hi); in GetSplitOp()
1084 GetExpandedInteger(Op, Lo, Hi); in GetSplitOp()
1086 GetExpandedFloat(Op, Lo, Hi); in GetSplitOp()
1114 GetExpandedInteger(Op, Lo, Hi); in GetExpandedOp()
[all …]
H A DLegalizeTypesGeneric.cpp59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
97 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
269 Hi = DAG.getLoad( in ExpandRes_NormalLoad()
385 SDValue Lo, Hi; in ExpandOp_BUILD_VECTOR() local
401 SDValue Lo, Hi; in ExpandOp_EXTRACT_ELEMENT() local
425 SDValue Lo, Hi; in ExpandOp_INSERT_VECTOR_ELT() local
472 SDValue Lo, Hi; in ExpandOp_NormalStore() local
[all …]
H A DLegalizeTypes.cpp778 Hi = getSDValue(Entry.second); in GetExpandedInteger()
789 AnalyzeNewValue(Hi); in SetExpandedInteger()
794 DAG.transferDbgValues(Op, Hi, 0, Hi.getValueSizeInBits(), false); in SetExpandedInteger()
807 Entry.second = getTableId(Hi); in SetExpandedInteger()
826 AnalyzeNewValue(Hi); in SetExpandedFloat()
853 AnalyzeNewValue(Hi); in SetSplitVector()
995 SDLoc dlHi(Hi); in JoinIntegers()
998 EVT HVT = Hi.getValueType(); in JoinIntegers()
1004 Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi); in JoinIntegers()
1005 Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi, in JoinIntegers()
[all …]
H A DLegalizeIntegerTypes.cpp458 Hi = BitConvertToInteger(Hi); in PromoteIntRes_BITCAST()
3282 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB()
3526 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, in ExpandIntRes_AssertSext()
3563 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi); in ExpandIntRes_BITREVERSE()
3571 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); in ExpandIntRes_BSWAP()
4671 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND()
4697 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND_INREG()
4740 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); in ExpandIntRes_TRUNCATE()
4988 Hi = DAG.getZeroExtendInReg(Hi, dl, in ExpandIntRes_ZERO_EXTEND()
5458 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, in ExpandIntOp_STORE()
[all …]
H A DLegalizeFloatTypes.cpp1272 SDValue Lo, Hi; in ExpandFloatResult() local
1273 Lo = Hi = SDValue(); in ExpandFloatResult()
1602 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
1615 Hi = N->getOperand(1); in ExpandFloatRes_FP_EXTEND()
1660 Hi = DAG.getNode(ISD::FREEZE, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FREEZE()
1754 Chain = Hi.getValue(1); in ExpandFloatRes_LOAD()
1828 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); in ExpandFloatRes_XINT_TO_FP()
1991 SDValue Lo, Hi; in ExpandFloatOp_FCOPYSIGN() local
2003 SDValue Lo, Hi; in ExpandFloatOp_FP_ROUND() local
2111 SDValue Lo, Hi; in ExpandFloatOp_STORE() local
[all …]
H A DLegalizeVectorTypes.cpp1374 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
1383 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
1400 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
1481 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, in SplitVecRes_INSERT_SUBVECTOR()
1781 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
1843 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi); in SplitVecRes_INSERT_VECTOR_ELT()
2326 Hi = DAG.getNode(Opcode, dl, HiVT, Hi, Flags); in SplitVecRes_UnaryOp()
2860 Hi = in SplitVecRes_VECTOR_SPLICE()
2910 Hi = in SplitVecRes_VP_REVERSE()
3261 Hi = BitConvertToInteger(Hi); in SplitVecOp_BITCAST()
[all …]
/freebsd-14.2/sys/contrib/dev/acpica/components/utilities/
H A Dutmath.c164 UINT32 Hi; member
216 Product.Part.Hi, Carry32); in AcpiUtShortMultiply()
221 Product.Part.Hi += Carry32; in AcpiUtShortMultiply()
308 OperandOvl.Part.Hi = 0; in AcpiUtShortShiftRight()
474 Quotient.Part.Hi, Remainder32); in AcpiUtShortDivide()
540 if (Divisor.Part.Hi == 0) in AcpiUtDivide()
546 Remainder.Part.Hi = 0; in AcpiUtDivide()
565 Quotient.Part.Hi = 0; in AcpiUtDivide()
597 if (Partial3.Part.Hi == 0) in AcpiUtDivide()
617 Remainder.Part.Hi = (UINT32) -((INT32) Remainder.Part.Hi); in AcpiUtDivide()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp87 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC) in INITIALIZE_PASS()
109 if (Hi.getOpcode() == RISCV::LUI) { in INITIALIZE_PASS()
142 Hi.getOperand(1).setOffset(Offset); in foldOffset()
143 if (Hi.getOpcode() != RISCV::AUIPC) in foldOffset()
201 foldOffset(Hi, Lo, TailAdd, OffLo); in foldLargeOffset()
222 foldOffset(Hi, Lo, TailAdd, Offset); in foldLargeOffset()
231 foldOffset(Hi, Lo, TailAdd, Offset); in foldLargeOffset()
330 foldOffset(Hi, Lo, Tail, Offset); in detectAndFoldOffset()
469 if (Hi.getOpcode() != RISCV::AUIPC) in foldIntoMemoryOps()
519 for (MachineInstr &Hi : MBB) { in runOnMachineFunction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h39 uint64_t Hi = 0; variable
43 DecoderUInt128(uint64_t Lo, uint64_t Hi = 0) : Lo(Lo), Hi(Hi) {} in Lo()
44 operator bool() const { return Lo || Hi; }
51 Hi |= SubBits >> 1 >> (63 - BitPosition); in insertBits()
53 Hi |= SubBits << (BitPosition - 64); in insertBits()
62 Val = Lo >> BitPosition | Hi << 1 << (63 - BitPosition); in extractBitsAsZExtValue()
64 Val = Hi >> (BitPosition - 64); in extractBitsAsZExtValue()
68 return DecoderUInt128(Lo & RHS.Lo, Hi & RHS.Hi);
75 return Lo == RHS.Lo && Hi == RHS.Hi;
78 return Lo != RHS.Lo || Hi != RHS.Hi;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A Daarch32.cpp80 uint32_t S = Hi & 0x0400; in decodeImmBT4BlT1BlxT2_J1J2()
83 uint32_t Imm10 = Hi & 0x03ff; in decodeImmBT4BlT1BlxT2_J1J2()
125 uint32_t Imm4 = Hi & 0x0f; in decodeImmMovtT1MovwT3()
217 : Hi{Writable.Hi}, Lo(Writable.Lo) {} in ThumbRelocation()
267 return (Hi & FixupInfo<K>::OpcodeMask.Hi) == FixupInfo<K>::Opcode.Hi && in checkOpcodeThumb()
347 uint16_t Hi = R.Hi & FixupInfo<Kind>::RegMask.Hi; in checkRegister() local
349 return Hi == Reg.Hi && Lo == Reg.Lo; in checkRegister()
361 assert((Mask.Hi & Reg.Hi) == Reg.Hi && (Mask.Lo & Reg.Lo) == Reg.Lo && in writeRegister()
363 R.Hi = (R.Hi & ~Mask.Hi) | Reg.Hi; in writeRegister()
377 assert((Mask.Hi & Imm.Hi) == Imm.Hi && (Mask.Lo & Imm.Lo) == Imm.Lo && in writeImmediate()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp144 uint64_t Lo, Hi; in readInstruction64() local
153 Hi = (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 0) | (Bytes[3] << 8); in readInstruction64()
156 Hi = (Bytes[0] << 24) | ((Bytes[1] & 0x0F) << 20) | ((Bytes[1] & 0xF0) << 12) | in readInstruction64()
160 Insn = Make_64(Hi, Lo); in readInstruction64()
170 uint64_t Insn, Hi; in getInstruction() local
199 Hi = (Bytes[12] << 0) | (Bytes[13] << 8) | (Bytes[14] << 16) | (Bytes[15] << 24); in getInstruction()
201 Hi = (Bytes[12] << 24) | (Bytes[13] << 16) | (Bytes[14] << 8) | (Bytes[15] << 0); in getInstruction()
203 Op.setImm(Make_64(Hi, Op.getImm())); in getInstruction()
/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DX86.cpp1734 Hi = SSE; in postMerge()
1874 Hi = Lo; in classify()
1897 Hi = Lo; in classify()
1959 Hi = Lo; in classify()
2010 Hi = merge(Hi, FieldHi); in classify()
2063 Hi = merge(Hi, FieldHi); in classify()
2140 Hi = merge(Hi, FieldHi); in classify()
2579 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && in classifyReturnType()
2633 switch (Hi) { in classifyReturnType()
2712 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && in classifyArgumentType()
[all …]
/freebsd-14.2/contrib/llvm-project/compiler-rt/lib/orc/
H A Dendianness.h59 uint16_t Hi = value << 8; in ByteSwap_16()
61 return Hi | Lo; in ByteSwap_16()
87 uint64_t Hi = ByteSwap_32(uint32_t(value)); in ByteSwap_64()
89 return (Hi << 32) | Lo; in ByteSwap_64()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch32.h165 constexpr HalfWords() : Hi(0), Lo(0) {} in HalfWords()
166 constexpr HalfWords(uint32_t Hi, uint32_t Lo) : Hi(Hi), Lo(Lo) { in HalfWords()
167 assert(isUInt<16>(Hi) && "Overflow in first half-word"); in HalfWords()
170 const uint16_t Hi; // First halfword member
187 bool (*checkOpcode)(uint16_t Hi, uint16_t Lo) = nullptr;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp342 uint32_t Hi = Hi_32(Val); in generateInstSeq() local
347 if (Lo > 0 && TmpSeq.size() + llvm::popcount(Hi) < Res.size()) { in generateInstSeq()
349 } else if (Lo < 0 && TmpSeq.size() + llvm::popcount(~Hi) < Res.size()) { in generateInstSeq()
351 Hi = ~Hi; in generateInstSeq()
355 while (Hi != 0) { in generateInstSeq()
356 unsigned Bit = llvm::countr_zero(Hi); in generateInstSeq()
358 Hi &= (Hi - 1); // Clear lowest set bit. in generateInstSeq()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h73 Hi, enumerator
416 SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty, in getAddrGlobalLargeGOT() local
418 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); in getAddrGlobalLargeGOT()
419 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, in getAddrGlobalLargeGOT()
433 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); in getAddrNonPIC() local
436 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), in getAddrNonPIC()
450 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); in getAddrNonPICSym64() local
463 DAG.getNode(MipsISD::Hi, DL, Ty, Hi)); in getAddrNonPICSym64()
H A DMipsSEISelDAGToDAG.cpp1167 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue(); in trySelect() local
1171 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32); in trySelect()
1173 if (Hi) in trySelect()
1190 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue(); in trySelect() local
1194 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32); in trySelect()
1196 if (Hi) in trySelect()
1205 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64), in trySelect()
1244 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32); in trySelect()
1265 if (Hi) in trySelect()
1306 const bool ResNonZero = Hi || Lo; in trySelect()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPISelLowering.cpp29 SDValue HiA = CDAG.getUnpack(MVT::v256i1, A, PackElem::Hi, AVL); in splitMaskArithmetic()
31 SDValue HiB = CDAG.getUnpack(MVT::v256i1, B, PackElem::Hi, AVL); in splitMaskArithmetic()
207 for (PackElem Part : {PackElem::Hi, PackElem::Lo}) { in splitPackedLoadStore()
213 if (Part == PackElem::Hi) in splitPackedLoadStore()
252 SDValue HiChain = SDValue(PartOps[(int)PackElem::Hi].getNode(), ChainResIdx); in splitPackedLoadStore()
264 PartOps[(int)PackElem::Hi], UpperPartAVL); in splitPackedLoadStore()
365 for (PackElem Part : {PackElem::Hi, PackElem::Lo}) { in splitVectorOp()
370 if (Part == PackElem::Hi) in splitVectorOp()
399 PartOps[(int)PackElem::Hi], UpperPartAVL); in splitVectorOp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp1153 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi); in LowerConstantPool()
1184 SDValue Hi = DAG.getTargetGlobalAddress( in LowerGlobalAddress() local
1188 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi); in LowerGlobalAddress()
1204 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi); in LowerBlockAddress()
1226 SDValue Hi = DAG.getTargetJumpTable( in LowerJumpTable() local
1230 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi); in LowerJumpTable()
1273 SDValue Hi = in LowerSHL_PARTS() local
1282 SDValue Ops[2] = {Lo, Hi}; in LowerSHL_PARTS()
1312 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1315 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/
H A DMCObjectStreamer.cpp149 static std::optional<uint64_t> absoluteSymbolDiff(const MCSymbol *Hi, in absoluteSymbolDiff() argument
151 assert(Hi && Lo); in absoluteSymbolDiff()
152 if (!Hi->getFragment() || Hi->getFragment() != Lo->getFragment() || in absoluteSymbolDiff()
153 Hi->isVariable() || Lo->isVariable()) in absoluteSymbolDiff()
156 return Hi->getOffset() - Lo->getOffset(); in absoluteSymbolDiff()
159 void MCObjectStreamer::emitAbsoluteSymbolDiff(const MCSymbol *Hi, in emitAbsoluteSymbolDiff() argument
163 if (std::optional<uint64_t> Diff = absoluteSymbolDiff(Hi, Lo)) in emitAbsoluteSymbolDiff()
165 MCStreamer::emitAbsoluteSymbolDiff(Hi, Lo, Size); in emitAbsoluteSymbolDiff()
168 void MCObjectStreamer::emitAbsoluteSymbolDiffAsULEB128(const MCSymbol *Hi, in emitAbsoluteSymbolDiffAsULEB128() argument
171 if (std::optional<uint64_t> Diff = absoluteSymbolDiff(Hi, Lo)) { in emitAbsoluteSymbolDiffAsULEB128()
[all …]
/freebsd-14.2/sys/contrib/device-tree/Bindings/sound/
H A Dtlv320adcx140.yaml140 0 - Hi-Z output
143 3 - Drive active low and Hi-Z
145 5 - Drive Hi-Z and active high
157 When set the device will set the Tx ASI output to a Hi-Z state for unused
179 0d - (default) Hi-Z output
182 3d - Drive active low and Hi-Z
184 5d - Drive Hi-Z and active high
H A Dcirrus,cs35l41.yaml70 Audio serial port SDOUT Hi-Z control. Sets the Hi-Z
73 1 = Hi-Z during unused slots but logic 0 while all transmit channels disabled
74 2 = (Default) Logic 0 during unused slots, but Hi-Z while all transmit channels disabled
75 3 = Hi-Z during unused slots and while all transmit channels disabled
/freebsd-14.2/lib/libc/nls/
H A Dca_ES.ISO8859-1.msg52 23 Hi ha massa arxius oberts al sistema
54 24 Hi ha massa arxius oberts
124 59 Hi ha massa refer�ncies: no es poden unir
130 62 Hi ha massa nivells d'enlla�os simb�lics
140 67 Hi ha massa processos
142 68 Hi ha massa usuaris
/freebsd-14.2/contrib/llvm-project/llvm/lib/IR/
H A DMDBuilder.cpp84 MDNode *MDBuilder::createRange(const APInt &Lo, const APInt &Hi) { in createRange() argument
85 assert(Lo.getBitWidth() == Hi.getBitWidth() && "Mismatched bitwidths!"); in createRange()
88 return createRange(ConstantInt::get(Ty, Lo), ConstantInt::get(Ty, Hi)); in createRange()
91 MDNode *MDBuilder::createRange(Constant *Lo, Constant *Hi) { in createRange() argument
93 if (Hi == Lo) in createRange()
97 return MDNode::get(Context, {createConstant(Lo), createConstant(Hi)}); in createRange()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp542 SDValue Lo(Hi.getNode(), 1); in LowerSMUL_LOHI()
543 SDValue Ops[] = { Lo, Hi }; in LowerSMUL_LOHI()
559 SDValue Lo(Hi.getNode(), 1); in LowerUMUL_LOHI()
560 SDValue Ops[] = { Lo, Hi }; in LowerUMUL_LOHI()
656 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
664 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
675 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
678 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); in TryExpandADDWithMul()
679 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH); in TryExpandADDWithMul()
720 SDValue Ignored(Hi.getNode(), 1); in ExpandADDSUB()
[all …]

1234567