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Searched refs:HasVSX (Results 1 – 10 of 10) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td1339 } // HasVSX, HasP8Vector
2448 // [HasVSX]
2449 // [HasVSX, IsBigEndian]
2451 // [HasVSX, NoP9Vector]
2456 // [HasVSX, NoP8Vector]
2457 // [HasVSX, HasP8Vector]
2471 // [HasVSX, HasP9Vector]
2921 } // HasVSX
3034 } // HasVSX, IsBigEndian
3187 } // HasVSX, NoP9Vector
[all …]
H A DPPCSubtarget.cpp114 if (HasSPE && (HasAltivec || HasVSX || HasFPU)) in initSubtargetFeatures()
H A DPPCInstrFuture.td54 let Predicates = [HasVSX, IsISAFuture] in {
H A DPPCInstrP10.td1912 let Predicates = [IsISA3_1, HasVSX] in {
2078 let Predicates = [IsISA3_1, HasVSX] in {
2115 let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
2375 let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
2409 let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in {
2422 let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in {
2446 let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in {
H A DPPC.td150 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
H A DPPCISelDAGToDAG.cpp4371 bool HasVSX, bool &Swap, bool &Negate) { in getVCmpInst() argument
4399 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP; in getVCmpInst()
4406 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP; in getVCmpInst()
4413 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP; in getVCmpInst()
H A DPPCInstrAltivec.td1323 // !HasVSX predicate. This essentially favours VSX over Altivec, in
H A DPPCISelLowering.cpp6959 bool HasVSX) { in getRegClassForSVT() argument
6973 return HasVSX ? &PPC::VSFRCRegClass : &PPC::F8RCRegClass; in getRegClassForSVT()
/freebsd-14.2/contrib/llvm-project/clang/lib/Basic/Targets/
H A DPPC.cpp40 HasVSX = true; in handleTargetFeatures()
397 if (HasVSX) in getTargetDefines()
680 .Case("vsx", HasVSX) in hasFeature()
H A DPPC.h64 bool HasVSX = false; variable