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Searched refs:HalfVT (Results 1 – 14 of 14) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h413 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
414 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
415 return HalfVT; in getHalfSizedIntegerVT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp368 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4() local
386 createUnpackShuffleMask(HalfVT, MaskLowTemp, true, false); in interleave8bitStride4()
387 createUnpackShuffleMask(HalfVT, MaskHighTemp, false, false); in interleave8bitStride4()
H A DX86ISelLowering.cpp6924 EVT HalfVT = in EltsFromConsecutiveLoads() local
8079 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in getHopForBuildVector() local
15161 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in getShuffleHalfVectors() local
15166 return DAG.getUNDEF(HalfVT); in getShuffleHalfVectors()
15179 SDValue Op1 = DAG.getUNDEF(HalfVT); in getShuffleHalfVectors()
15209 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in lowerShuffleWithUndefHalf() local
20005 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in LowerAVXExtend() local
20018 OpHi = DAG.getBitcast(HalfVT, OpHi); in LowerAVXExtend()
24268 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in LowerEXTEND_VECTOR_INREG() local
24278 Hi = DAG.getNode(Opc, dl, HalfVT, Hi); in LowerEXTEND_VECTOR_INREG()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1989 SDValue One = DAG.getConstant(1, DL, HalfVT); in LowerUDIVREM64()
1990 SDValue Zero = DAG.getConstant(0, DL, HalfVT); in LowerUDIVREM64()
1995 std::tie(LHS_Lo, LHS_Hi) = DAG.SplitScalar(LHS, DL, HalfVT, HalfVT); in LowerUDIVREM64()
1999 std::tie(RHS_Lo, RHS_Hi) = DAG.SplitScalar(RHS, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2004 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
2059 DAG.SplitScalar(Mulhi1, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2072 DAG.SplitScalar(Mulhi2, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2085 std::tie(Mul3_Lo, Mul3_Hi) = DAG.SplitScalar(Mul3, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2162 const unsigned halfBitWidth = HalfVT.getSizeInBits(); in LowerUDIVREM64()
2166 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT); in LowerUDIVREM64()
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H A DSIISelLowering.cpp7031 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), in lowerBUILD_VECTOR() local
7033 MVT HalfIntVT = MVT::getIntegerVT(HalfVT.getSizeInBits()); in lowerBUILD_VECTOR()
7042 SDValue Lo = DAG.getBuildVector(HalfVT, SL, LoOps); in lowerBUILD_VECTOR()
7043 SDValue Hi = DAG.getBuildVector(HalfVT, SL, HiOps); in lowerBUILD_VECTOR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp1042 EVT HalfVT = in SplitInteger() local
1044 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
H A DLegalizeIntegerTypes.cpp4767 EVT HalfVT = LHSLow.getValueType(); in ExpandIntRes_XMULO() local
4769 SDVTList VTHalfWithO = DAG.getVTList(HalfVT, BitVT); in ExpandIntRes_XMULO()
4771 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT); in ExpandIntRes_XMULO()
4782 SDValue HighSum = DAG.getNode(ISD::ADD, dl, HalfVT, One, Two); in ExpandIntRes_XMULO()
5033 EVT HalfVT = In1.getValueType(); in ExpandIntRes_FunnelShift() local
5042 unsigned HalfVTBits = HalfVT.getScalarSizeInBits(); in ExpandIntRes_FunnelShift()
5056 Lo = DAG.getNode(Opc, DL, HalfVT, Select2, Select1, NewShAmt); in ExpandIntRes_FunnelShift()
5057 Hi = DAG.getNode(Opc, DL, HalfVT, Select3, Select2, NewShAmt); in ExpandIntRes_FunnelShift()
5063 EVT HalfVT = in ExpandIntRes_VSCALE() local
5068 APInt One(HalfVT.getSizeInBits(), 1); in ExpandIntRes_VSCALE()
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H A DTargetLowering.cpp1839 if (isNarrowingProfitable(VT, HalfVT) && in SimplifyDemandedBits()
1840 isTypeDesirableForOp(ISD::SHL, HalfVT) && in SimplifyDemandedBits()
1841 isTruncateFree(VT, HalfVT) && isZExtFree(HalfVT, VT) && in SimplifyDemandedBits()
1853 ShAmt, HalfVT, dl, TLO.LegalTypes()); in SimplifyDemandedBits()
1947 if (isNarrowingProfitable(VT, HalfVT) && in SimplifyDemandedBits()
1948 isTypeDesirableForOp(ISD::SRL, HalfVT) && in SimplifyDemandedBits()
1949 isTruncateFree(VT, HalfVT) && isZExtFree(HalfVT, VT) && in SimplifyDemandedBits()
1955 ShAmt, HalfVT, dl, TLO.LegalTypes()); in SimplifyDemandedBits()
2373 EVT HalfVT = Op.getOperand(0).getValueType(); in SimplifyDemandedBits() local
10631 Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi); in expandVecReduce()
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H A DLegalizeVectorTypes.cpp3872 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, in SplitVecOp_TruncateHelper() local
3879 HalfLo = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
3881 HalfHi = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
3888 HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); in SplitVecOp_TruncateHelper()
3889 HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); in SplitVecOp_TruncateHelper()
H A DSelectionDAGBuilder.cpp196 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
199 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, PartVT, HalfVT, V, in getCopyFromParts()
202 PartVT, HalfVT, V, InChain); in getCopyFromParts()
204 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
205 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
H A DDAGCombiner.cpp11041 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), BW / 2); in visitBSWAP() local
11044 (ShAmt->getZExtValue() % 16) == 0 && TLI.isTypeLegal(HalfVT) && in visitBSWAP()
11045 TLI.isTruncateFree(VT, HalfVT) && in visitBSWAP()
11046 (!LegalOperations || hasOperation(ISD::BSWAP, HalfVT))) { in visitBSWAP()
11051 Res = DAG.getZExtOrTrunc(Res, DL, HalfVT); in visitBSWAP()
11052 Res = DAG.getNode(ISD::BSWAP, DL, HalfVT, Res); in visitBSWAP()
24631 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), in foldShuffleOfConcatUndefs() local
24633 if (!TLI.isShuffleMaskLegal(Mask0, HalfVT) || in foldShuffleOfConcatUndefs()
24634 !TLI.isShuffleMaskLegal(Mask1, HalfVT)) in foldShuffleOfConcatUndefs()
24641 SDValue Shuf0 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask0); in foldShuffleOfConcatUndefs()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14128 EVT HalfVT = Lo.getValueType(); in getVectorBitwiseReduce() local
14862 auto *HalfVT = cast<FixedVectorType>(HalfV->getType()); in areExtractShuffleVectors() local
17055 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), in performMulVectorCmpZeroCombine() local
19002 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), in performVectorAddSubExtCombine() local
20742 unsigned NumElts = HalfVT.getVectorNumElements(); in splitStores()
20879 EVT BCVT = MVT::Other, HalfVT = MVT::Other; in performUzpCombine() local
20885 HalfVT = MVT::v8i8; in performUzpCombine()
20889 HalfVT = MVT::v4i16; in performUzpCombine()
20893 HalfVT = MVT::v2i32; in performUzpCombine()
20900 DAG.getUNDEF(HalfVT)); in performUzpCombine()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17993 MVT ExtVT, HalfVT; in PerformMinMaxCombine() local
17995 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
17998 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
18006 DAG.getNode(ARMISD::VQMOVNs, DL, HalfVT, DAG.getUNDEF(HalfVT), in PerformMinMaxCombine()
18033 MVT HalfVT; in PerformMinMaxCombine() local
18036 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
18039 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
18047 DAG.getNode(ARMISD::VQMOVNu, DL, HalfVT, DAG.getUNDEF(HalfVT), N0, in PerformMinMaxCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4914 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in lowerVECTOR_SHUFFLE() local
4920 EvenV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, EvenV, in lowerVECTOR_SHUFFLE()
4925 OddV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, OddV, in lowerVECTOR_SHUFFLE()